F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

ID 720987
Date 7/08/2024
Public
Document Table of Contents

3.3.3.1.1. Run-time Reset Sequence—TX

Figure 11. Run-time Reset Sequence—TX

The figure above illustrates the following run-time TX reset sequence:

  1. Assert i_tx_rst_n.
  2. o_tx_lanes_stable deasserts, indicating that the TX datapath is no longer operational.
  3. o_tx_pll_locked deasserts.
  4. o_tx_reset_ack asserts, indicating that the TX datapath is fully in reset.
  5. You then deassert i_tx_rst_n to bring TX out of reset.
  6. o_tx_pll_locked asserts as the TX PLL locks to the reference clock.
  7. o_tx_lanes_stable asserts.