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1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
4. Interface Signals Description
5. Configuration Registers Description
6. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
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3.3.3.1.1. Run-time Reset Sequence—TX
Figure 11. Run-time Reset Sequence—TX
The figure above illustrates the following run-time TX reset sequence:
- Assert i_tx_rst_n.
- o_tx_lanes_stable deasserts, indicating that the TX datapath is no longer operational.
- o_tx_pll_locked deasserts.
- o_tx_reset_ack asserts, indicating that the TX datapath is fully in reset.
- You then deassert i_tx_rst_n to bring TX out of reset.
- o_tx_pll_locked asserts as the TX PLL locks to the reference clock.
- o_tx_lanes_stable asserts.