F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

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ID 720987
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example 4. Interface Signals Description 5. Configuration Registers Description 6. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP Design Example User Guide Archives 7. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design 2.3. Compiling and Simulating the Design 2.4. Compiling and Testing the Design in Hardware 2.5. Signal Tap Debugging
2.2. Generating the Design x
2.2.1. Procedure 2.2.2. Design Example Parameters
2.3. Compiling and Simulating the Design x
2.3.1. Procedure 2.3.2. Testbench
2.4. Compiling and Testing the Design in Hardware x
2.4.1. Procedure 2.4.2. Hardware Setup
2.5. Signal Tap Debugging x
2.5.1. Signal Tap Debug Signals
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Interface Signals 3.7. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme
3.3.3. Reset Scheme x
3.3.3.1. Reset Sequence
3.3.3.1. Reset Sequence x
3.3.3.1.1. Run-time Reset Sequence—TX 3.3.3.1.2. Run-time Reset Sequence—RX 3.3.3.1.3. Run-time Reset Sequence—TX + RX
3.4. Simulation x
3.4.1. Test Case—Design Example with the IEEE 1588v2 Feature 3.4.2. Test Case—Design Example without the IEEE 1588v2 Feature
3.5. Hardware Testing x
3.5.1. Test Procedure 3.5.2. Design Constraints
4. Interface Signals Description x
4.1. Clock and Reset Interface Signals 4.2. Avalon® Memory-Mapped Interface Signals 4.3. Avalon® Streaming Interface Signals 4.4. PHY Interface Signals 4.5. Status Interface 4.6. IEEE 1588v2 Timestamp Interface Signals 4.7. Packet Classifier Interface Signals 4.8. TOD Interface Signals
5. Configuration Registers Description x
5.1. Register Access Definition 5.2. Low Latency Ethernet 10G MAC 5.3. PHY 5.4. TOD
5.3. PHY x
5.3.1. 1G/2.5G/5G/10G Multirate PHY
1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
4. Interface Signals Description
5. Configuration Registers Description
6. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

4.5. Status Interface

Table 15.  Status Interface Signals
Signal Direction Description

rx_block_lock

Out Asserted when the link synchronization is successful.

led_an

Out Asserted when auto-negotiation is completed.

channel_tx_ready

channel_rx_ready

o_lanes_stable

o_rx_pcs_ready

Out Asserted when the channel is ready for data transmission.
xgmii_rx_link_fault_status Out This signal indicates the status of the received data bytes. High indicates fault data bytes.
o_rst_ack_n Out Active-low asynchronous acknowledgement signal for the i_rst_n reset. Do not deassert i_rst_n reset until the o_rst_ack_n asserts.
o_tx_rst_ack_n Out Active-low asynchronous acknowledgement signal for the i_tx_rst_n reset. Do not deassert i_tx_rst_n reset until the o_tx_rst_ack_n asserts.
o_rx_rst_ack_n Out Active-low asynchronous acknowledgement signal for the i_rx_rst_n reset. Do not deassert i_rx_rst_n reset until the o_rx_rst_ack_n asserts.
o_tx_lanes_stable Out Active-high asynchronous status signal for the TX datapath. Asserts when the TX datapath is ready to send data. Deassert when i_tx_rst_n/i_rst_n signal asserts.
o_rx_pcs_ready Out Active-high asynchronous status signal for the RX datapath. Asserts when the RX datapath is ready to receive data. Deasserts when i_rx_rst_n/i_rst_n signal asserts.
o_cdr_lock Out This signal indicates that the recovered clocks are locked to data.
o_tx_pll_locked Out Indicates TX serdes PLLs are locked. Do not use o_clk_tx_div until o_tx_pll_locked is high.
tod_sampling_pll_locked Out This signal indicates the lock status of TOD Synchronizer sampling clock PLL.
dl_sampling_pll_locked Out This signal indicates the lock status of deterministic latency measurement sampling clock PLL.
Level Two Title