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1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
4. Interface Signals Description
5. Configuration Registers Description
6. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
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3.5.1. Test Procedure
After running the command: source main.tcl, a list of available JTAG Masters is displayed. By default, the first JTAG master is selected. To select the JTAG master for Agilex™ 7 devices, run this command: set_jtag <JTAG Master>. Example: set_jtag 1.
Follow these steps to test the design examples in hardware:
- Run the following command in the system console to start the test.
TEST_EXT_LB <channel> <speed> <burst_size>
Example: TEST_EXT_LB 0 10G 80000000
Table 8. Command Parameters Parameter Valid Values Description channel 0, 1 The channel number to test. speed 10M, 100M, 1G, 2P5G, 5G, 10G The PHY speed. burst_size An integer value The number of packets to generate for the test. - When the test is completed, observe the output displayed. The following diagrams show excerpts of the output, which shows that the Ethernet packet monitor block receives the same number of packets generated without error, and the TX and RX statistics counters.
Figure 16. Sample Test Output—Ethernet Packet Monitor
Figure 17. Sample Test Output—Statistics Counters