Visible to Intel only — GUID: nfa1462243383929
Ixiasoft
1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
4. Interface Signals Description
5. Configuration Registers Description
6. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
Visible to Intel only — GUID: nfa1462243383929
Ixiasoft
3.2. Hardware and Software Requirements
Altera uses the following hardware and software to test the design example in a Linux system:
- Quartus® Prime Pro Edition software
- ModelSim* -AE, ModelSim* -SE, VCS, and Xcelium* simulators
- VCS simulator
- For hardware testing:
- Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (AGIB027R31B1E1V)
- QSFP-DD Loopback Module connected to J27(QSFP-DD Connector)
- Amphenol QSFP-DD 400G LOOPBACK ADAPTER MODULE 0dB (SF-NLNAMB0001-0001)