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2.1. Port Numbering Scheme
2.2. Clock Signals
2.3. Reset Signals
2.4. Fractured MAC Segmented Interface for FGT Transceivers
2.5. Fractured MAC Segmented Interface for FHT Transceivers
2.6. Fractured MAC Avalon ST Client Interface for FGT Transceivers
2.7. Fractured MAC Avalon ST Client Interface for FHT Transceivers
2.8. Fractured MII PCS-Only Interface for FGT Transceivers
2.9. Fractured MII PCS-Only Interface for FHT Transceivers
2.10. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers
2.11. Fractured PCS66 Interface for OTN/FlexE for FHT Transceivers
2.12. MAC Flow Control Interface
2.13. Status Interface
2.14. Avalon® Memory-Mapped Reconfiguration Interfaces
2.15. Auto-Negotiation and Link Training Interface
2.16. Precision Time Protocol Interface
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2. Interface Overview
This section describes various interfaces of the F-Tile Ethernet Multirate Intel FPGA IP core.
Figure 2. F-Tile Ethernet Multirate IP Core Interface Diagram
Section Content
Port Numbering Scheme
Clock Signals
Reset Signals
Fractured MAC Segmented Interface for FGT Transceivers
Fractured MAC Segmented Interface for FHT Transceivers
Fractured MAC Avalon ST Client Interface for FGT Transceivers
Fractured MAC Avalon ST Client Interface for FHT Transceivers
Fractured MII PCS-Only Interface for FGT Transceivers
Fractured MII PCS-Only Interface for FHT Transceivers
Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers
Fractured PCS66 Interface for OTN/FlexE for FHT Transceivers
MAC Flow Control Interface
Status Interface
Avalon Memory-Mapped Reconfiguration Interfaces
Auto-Negotiation and Link Training Interface
Precision Time Protocol Interface