Visible to Intel only — GUID: zcw1646314242441
Ixiasoft
2.1. Port Numbering Scheme
2.2. Clock Signals
2.3. Reset Signals
2.4. Fractured MAC Segmented Interface for FGT Transceivers
2.5. Fractured MAC Segmented Interface for FHT Transceivers
2.6. Fractured MAC Avalon ST Client Interface for FGT Transceivers
2.7. Fractured MAC Avalon ST Client Interface for FHT Transceivers
2.8. Fractured MII PCS-Only Interface for FGT Transceivers
2.9. Fractured MII PCS-Only Interface for FHT Transceivers
2.10. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers
2.11. Fractured PCS66 Interface for OTN/FlexE for FHT Transceivers
2.12. MAC Flow Control Interface
2.13. Status Interface
2.14. Avalon® Memory-Mapped Reconfiguration Interfaces
2.15. Auto-Negotiation and Link Training Interface
2.16. Precision Time Protocol Interface
Visible to Intel only — GUID: zcw1646314242441
Ixiasoft
2.15. Auto-Negotiation and Link Training Interface
To enable the auto-negotiation and link training interface, you specify a virtual link at a top-level output port. The port is only available when you turn on the Enable auto-negotiation and link training parameter in the F-Tile Ethernet Multirate Intel FPGA IP parameter editor.
During the compilation, the Quartus® Prime software automatically connects the F-Tile Ethernet Multirate Intel FPGA IP design with the F-Tile Auto-Negotiation and Link Training Intel FPGA IP.
Number of Ports | Signal Name |
---|---|
1, 2, or 4 | o_anlt_link[NUM_OF_PORTS-1:0] where NUM_OF_PORTS is the maximum number of ports supported in a reconfiguration group |