2.2. Clock Signals
The Ethernet Multirate IP core uses the o_clk_pll common system PLL clock for all ports within a reconfiguration group.
The i_reconfig_clk input is a common clock for the Avalon® memory-mapped interfaces of all ports within a reconfiguration group. You must use the same reconfiguration clock in the F-Tile Dynamic Reconfiguration IP core and all F-Tile Ethernet Multirate IP core instances targeting a particular tile.
- The i_clk_ref and the i_clk_sys clocks drives the IP core.
- The output clock o_clk_pll drives both the i_clk_rx and the i_clk_tx input signals.
Signal Name | Number of Ports | I/O Direction | Description |
---|---|---|---|
Clock Inputs | |||
i_clk_tx | 1, 2, or 4 | Input | TX datapath clock This clock drives the active TX interface for the port. This clock source is: o_clk_pll clock unless you enabled Enable asynchronous adapter clocks parameter. |
i_clk_rx | 1, 2, or 4 | Input | RX datapath clock This clock drives the active RX interface for the port. This clock source is: o_clk_pll clock unless you enabled Enable asynchronous adapter clocks parameter. |
i_reconfig_clk | 1, 2, or 4 | Input | Avalon® memory-mapped interface reconfiguration clock The interface uses this clock to access control status registers (CSRs). The clock supports 100 to 250 MHz frequency. When PTP is enabled, the i_reconfig_clk frequency supports the range of 100 to 250 MHz. |
i_clk_ref | 1, 2, or 4 | Input | PMA reference clock
F-Tile Reference and System PLL Clock Intel® FPGA IP drives this clock.
The clock source depends on the PMA selection.
Unless the Custom cadence parameter is enabled, the clock must be PPM matched to the i_clk_sys clock. |
i_clk_pll | 1, 2, or 4 | Input | PTP-related datapath clock This clock drives the internal datapath clock for the port when both, Enable IEEE 1588 PTP and Enable asynchronous adapter clocks parameters, are enabled. This clock source is the o_clk_pll output of the PTP tile adapter. You must use a single clock source when using a multiple PTP ports in your design.
Supports the following frequencies:
When Enable IEEE 1588 PTP parameter is disabled, connect this port to 1'b0. |
i_clk_sys | 1, 2, or 4 | Input | Ethernet system clock F-Tile Reference and System PLL Clocks Intel® FPGA IP drives this clock.
Unless Custom cadence parameter is enabled, the clock frequency depends on the FEC type:
You must specify this frequency in the F-Tile Ethernet Multirate Intel® FPGA IP System PLL frequency IP parameter and in the F-Tile Reference and System PLL Clocks Intel® FPGA IP Mode of system PLL IP parameter.
Note: The i_clk_sys is a virtual signal. In simulation, the signal displays as 0.
Connect to the out_systempll_clk_i signal from the F-Tile Reference and System PLL Clocks Intel® FPGA IP. |
Clock Outputs | |||
o_clk_pll | 1, 2, or 4 | Output | System PLL clock Clock derived from the F-Tile System PLL associated with the Ethernet IP port. The o_clk_pll frequency is equal to PLL frequency divided by 2. The following shows the o_clk_pll frequency unless you enabled custom system PLL frequency.
Supports the following frequencies:
|
Signal Name | Number of Ports | I/O Direction | Description |
---|---|---|---|
o_p0_clk_tx_div | 1, 2, or 4 | Output |
Supports the following frequencies:
Clock recovered from the TX SERDES rate divided by either 33/66/68, depending on the FEC mode and Ethernet mode parameters. The o_clk_tx_div is equal to:
|
o_p0_clk_rec_div64 | 1, 2, or 4 | Output |
Supports the following frequencies:
Clock derived from RX recovered clock, divided by 64. |
o_p0_clk_rec_div | 1, 2, or 4 | Output |
Supports the following frequencies:
Clock derived from the RX recovered clock divided by either 33/66/68, depending on the FEC mode parameter. The o_clk_rec_div is equal to:
|
o_p1_clk_tx_div | 2 or 4 | Output | Same as the o_p0_clk_tx_div signal description |
o_p1_clk_rec_div64 | 2 or 4 | Output | Same as the o_p0_clk_rec_div64 signal description |
o_p1_clk_rec_div | 2 or 4 | Output | Same as the o_p0_clk_rec_div signal description |
o_p2_clk_tx_div | 4 | Output | Same as the o_p0_clk_tx_div signal description |
o_p2_clk_rec_div64 | 4 | Output | Same as the o_p0_clk_rec_div64 signal description |
o_p2_clk_rec_div | 4 | Output | Same as the o_p0_clk_rec_div signal description |
o_p3_clk_tx_div | 4 | Output | Same as the o_p0_clk_tx_div signal description |
o_p3_clk_rec_div64 | 4 | Output | Same as the o_p0_clk_rec_div64 signal description |
o_p3_clk_rec_div | 4 | Output | Same as the o_p0_clk_rec_div signal description |
The locked status output is common since all ports in the reconfiguration group share the same system PLL clock. The transceiver PLL and RX CDR lock signals are port-specific dependent on the Number of Ports setting.
Signal Name | Number of Ports | I/O Direction | Description |
---|---|---|---|
o_sys_pll_locked | 1, 2, or 4 | Output | Indicates the locked system PLL. Do not use the o_clk_pll clock until the o_sys_pll_locked clock is high. |
o_p0_tx_pll_locked | 1, 2, or 4 | Output | Indicates the TX PLL driving clock signal from the core is locked. Do not use the o_clk_tx_div clock until the o_p0_tx_pll_locked clock is high. |
o_p0_cdr_lock | 1, 2, or 4 | Output | Indicates that the recovered clocks are locked to data. Do not use the o_clk_rec_div64 or o_clk_rec_div clocks until the o_p0_cdr_lock clock is high. |
o_p1_tx_pll_locked | 2 or 4 | Output | If you set the number of ports to 2 or 4, indicates the TX PLL driving clock signal from the core port1 is locked. Do not use the o_clk_tx_div clock until the o_p1_tx_pll_locked clock is high. |
o_p1_cdr_lock | 2 or 4 | Output | If you set the number of ports to 2 or 4, indicates that the recovered clocks from port 1 are locked to data. Do not use the o_clk_rec_div64 or o_clk_rec_div clocks until the o_p1_cdr_lock clock is high. |
o_p2_tx_pll_locked | 4 | Output | If you set the number of ports to 4, indicates the TX PLL driving clock signal from the core port2 is locked. Do not use the o_clk_tx_div clock until the o_p2_tx_pll_locked clock is high. |
o_p2_cdr_lock | 4 | Output | If you set the number of ports to 4, indicates that the recovered clocks from port 2 are locked to data. Do not use the o_clk_rec_div64 or o_clk_rec_div clocks until the o_p2_cdr_lock clock is high. |
o_p3_tx_pll_locked | 4 | Output | If you set the number of ports to 4, indicates the TX PLL driving clock signal from the core port3 is locked. Do not use the o_clk_tx_div clock until the o_p3_tx_pll_locked clock is high. |
o_p3_cdr_lock | 4 | Output | If you set the number of ports to 4, indicates that the recovered clocks from port 3 are locked to data. Do not use the o_clk_rec_div64 or o_clk_rec_div clocks until the o_p3_cdr_lock clock is high. |