Visible to Intel only — GUID: eyx1646268266438
Ixiasoft
Visible to Intel only — GUID: eyx1646268266438
Ixiasoft
2.14. Avalon® Memory-Mapped Reconfiguration Interfaces
- Ethernet reconfiguration Avalon® memory-mapped interface access the hard and soft IP CSRs. Each port instantiates one interface.
- Transceiver reconfiguration Avalon® memory-mapped interface accesses the transceiver registers. Each transceiver lane instantiates one interface.
Number of Ports | Signal Name |
---|---|
1 | Port 0: i_p0_reconfig_eth_addr[13:0] i_p0_reconfig_eth_read i_p0_reconfig_eth_write i_p0_reconfig_eth_byteenable[3:0] o_p0_reconfig_eth_readdata[31:0] o_p0_reconfig_eth_readdata_valid i_p0_reconfig_eth_writedata[31:0] o_p0_reconfig_eth_waitrequest |
2 | Port 0: i_p0_reconfig_eth_addr[13:0] i_p0_reconfig_eth_read i_p0_reconfig_eth_write i_p0_reconfig_eth_byteenable[3:0] o_p0_reconfig_eth_readdata[31:0] o_p0_reconfig_eth_readdata_valid i_p0_reconfig_eth_writedata[31:0] o_p0_reconfig_eth_waitrequest Port 1: i_p1_reconfig_eth_addr[13:0] i_p1_reconfig_eth_read i_p1_reconfig_eth_write i_p1_reconfig_eth_byteenable[3:0] o_p1_reconfig_eth_readdata[31:0] o_p1_reconfig_eth_readdata_valid i_p1_reconfig_eth_writedata[31:0] o_p1_reconfig_eth_waitrequest |
4 | Port 0: i_p0_reconfig_eth_addr[13:0] i_p0_reconfig_eth_read i_p0_reconfig_eth_write i_p0_reconfig_eth_byteenable[3:0] o_p0_reconfig_eth_readdata[31:0] o_p0_reconfig_eth_readdata_valid i_p0_reconfig_eth_writedata[31:0] o_p0_reconfig_eth_waitrequest Port 1: i_p1_reconfig_eth_addr[13:0] i_p1_reconfig_eth_read i_p1_reconfig_eth_write i_p1_reconfig_eth_byteenable[3:0] o_p1_reconfig_eth_readdata[31:0] o_p1_reconfig_eth_readdata_valid i_p1_reconfig_eth_writedata[31:0] o_p1_reconfig_eth_waitrequest Port 2: i_p2_reconfig_eth_addr[13:0] i_p2_reconfig_eth_read i_p2_reconfig_eth_write i_p2_reconfig_eth_byteenable[3:0] o_p2_reconfig_eth_readdata[31:0] o_p2_reconfig_eth_readdata_valid i_p2_reconfig_eth_writedata[31:0] o_p2_reconfig_eth_waitrequest Port 3: i_p3_reconfig_eth_addr[13:0] i_p3_reconfig_eth_read i_p3_reconfig_eth_write i_p3_reconfig_eth_byteenable[3:0] o_p3_reconfig_eth_readdata[31:0] o_p3_reconfig_eth_readdata_valid i_p3_reconfig_eth_writedata[31:0] o_p3_reconfig_eth_waitrequest |
For information about the transceiver reconfiguration Avalon® memory-mapped interface, refer to the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide.