F-Tile Ethernet Multirate Intel® FPGA IP User Guide

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ID 714307
Date 5/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile Ethernet Multirate Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide
1. Introduction x
1.1. Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation 1.7. F-Tile Ethernet Multirate IP Core Features and Constraints 1.8. F-Tile Ethernet Multirate IP Core Concepts
1.8. F-Tile Ethernet Multirate IP Core Concepts x
1.8.1. Reconfiguration Group 1.8.2. Base Profile 1.8.3. Secondary Profile 1.8.4. Secondary Profile Group 1.8.5. Startup Profile 1.8.6. Supported Reconfiguration Groups 1.8.7. PTP Timestamp Accuracy Support 1.8.8. Transceiver Lane Mapping
2. Interface Overview x
2.1. Port Numbering Scheme 2.2. Clock Signals 2.3. Reset Signals 2.4. Fractured MAC Segmented Interface for FGT Transceivers 2.5. Fractured MAC Segmented Interface for FHT Transceivers 2.6. Fractured MAC Avalon ST Client Interface for FGT Transceivers 2.7. Fractured MAC Avalon ST Client Interface for FHT Transceivers 2.8. Fractured MII PCS-Only Interface for FGT Transceivers 2.9. Fractured MII PCS-Only Interface for FHT Transceivers 2.10. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers 2.11. Fractured PCS66 Interface for OTN/FlexE for FHT Transceivers 2.12. MAC Flow Control Interface 2.13. Status Interface 2.14. Avalon® Memory-Mapped Reconfiguration Interfaces 2.15. Auto-Negotiation and Link Training Interface 2.16. Precision Time Protocol Interface
2.16. Precision Time Protocol Interface x
2.16.1. PTP Clock Interface 2.16.2. Time-of-Day Interface 2.16.3. TX 2-Step Timestamp Interface 2.16.4. TX 1-Step Timestamp Interface 2.16.5. RX Timestamp Interface 2.16.6. PTP Status Interface 2.16.7. PTP Tile Interface
4. Designing with the IP Core x
4.1. Specifying the IP Core Parameters and Options 4.2. Generated File Structure
4.1. Specifying the IP Core Parameters and Options x
4.1.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Precision Time Protocol
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Ethernet Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide

5. Block Description

The following block diagram shows the interconnections of F-tile Ethernet Multirate IP instances that are used as power up instance, and profile instances:
Figure 15. Block Diagram

The F-tile is connected to the FPGA fabric using Intel's embedded multi-die interconnect bridge (EMIB) technology. The EMIB Deskew block corrects for possible skew over the EMIB interfaces between the main FPGA die and the F-Tile. Typically, the 40GE/50GE/100GE/200GE/400GE ports access the EMIB Deskew block. The 10GE/25GE ports that use PTP can also access this block.

The TX/RX Data Path (DP) mapping functions map the Ethernet IP signals to the EMIB datapath.

The PTP soft component logic block enables the PTP interface. The block performs the soft logic operations required for the F-Tile timestamp system for 1588 PTP support and connects to the time-of-day (TOD) module.

The PCS interface and the PCS66 interface follows the path through the EMIB Deskew and DP Mapping stages. The interface does not use adapters.

The Auto-negotiation and Link Training (AN/LT) port connects to a separate F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP. When enabled, the IP provides the status and control information.

The Reconfiguration and reset logic implement the reconfiguration interfaces and resets for the core, respectively.

Avalon® memory-mapped interface (Avalon MM) Adapters communicate with the F-tile raw Avalon® memory-mapped interface, allowing an 8-to-32 bit conversion on the transactions.

Optional Debug Master Endpoints instantiate the Avalon MM interfaces via GUI options to enable Transceiver Toolkit and Ethernet Toolkit software utilities. This feature is planned for future release.


Section Content
Precision Time Protocol

Level Two Title