| 2024.05.01 |
24.1 |
11.0.0 |
Made the following changes:
- Removed the following TX Datapath Clock description from i_clk_tx signal.
- o_clk_pll of the PTP tile adapter when Enable IEEE 1588 PTP parameter is enabled
- Removed the following RX Datapath Clock description from i_clk_rx signal.
- o_clk_pll of the PTP tile adapter when Enable IEEE 1588 PTP parameter is enabled
|
| 2024.04.01 |
24.1 |
11.0.0 |
Made the following changes:
- Added Agilex™ 9 device family support.
- Removed the restrictions on PTP support for Agilex™ 7 041 devices in Device Speed Grade Support.
|
| 2024.02.01 |
23.4 |
9.0.0 |
Made the following changes in Parameters section:
- Added a note about the calculations needed to bound the TX Pre-emphasis settings in FHT TX Analog Parameter Options table.
- Added a link to F-Tile Architecture and PMA and FEC Direct PHY IP User Guide.
|
| 2023.12.04 |
23.4 |
9.0.0 |
- Updated resource utilization table due to changes from Nios II to Nios V.
- Added the following in Parameters tab:
- Enable debug endpoint for transceiver toolkit under Configure, Debug and Extension Options tab.
- Enable debug endpoint for Ethernet toolkit.
- Removed Include Deterministic Latency Interface from the IP Parameter GUI and section.
- Auto-Negotiation and Link Training options.
- Analog Parameters options tab as well as the image in Parameters:
- Added Analog Parameter options for FGT PMA table under Analog parameters Options tab.
- Added FGT TX Equalization (EQ) PM (N=0-32) table.
- Added FGT RX Analog Parameter Options table.
- Added Analog Parameter Options for FHT PMA table under Analog parameters Options tab.
- Added FHT TX Analog Parameter Options table.
- Added FHT RX Analog Parameter Options table.
- Updated F-Tile Ethernet Multirate Intel® FPGA IP Parameter Editor: IP Tab GUI in Parameters.
- Updated Stop TX traffic when link partner sends PAUSE in Parameters.
- Added new IP parameter: Enable IPXACT in Parameters.
|
| 2023.04.03 |
23.1 |
6.0.0 |
- Added "All device transceiver and core speed grades do not support all dynamic reconfiguration profiles" in Device Speed Grade Support.
- Added hyperlink to Device Speed Grade Support in the F-tile Ethernet Intel FPGA Hard IP User Guide.
- Updated features and limitations in the F-Tile Ethernet Multirate IP Core Features and Constraints.
- Added 100GE, 200GE, and 400GE Ethernet rate for advanced timestamp accuracy mode in Parameters: PTP Options Tab.
- Removed the following topics in Designing with the IP Core section:
- Installing and Licensing Intel® FPGA IP Cores
- Intel® FPGA IP Evaluation Mode
- Added the following in Configuration Registers:
- The F-tile Ethernet Multirate IP core specific registers are all "Read-Write" capable
- Byte addresses can be converted to word addresses by shifting 2 bits to the right(divide by 4).
- Updated the product family name to Intel Agilex 7.
|
| 2022.12.19 |
22.4 |
5.0.0 |
Added the following in Parameters section:
- Added PTP limitations when using FM4 devices in Device Speed Grade Support.
- Include 32-bit soft CWBIN counters parameter.
- PTP support for MAC Avalon ST client interface parameter.
- PTP logic resource optimization.
- Reconfig Clock Frequency.
- Added the IP parameter Editor: PTP options tab image in Parameters.
- Added a new register preamble_passthrough[3:0] with offset 0x20C in Configuration Registers section.
|
| 2022.10.20 |
22.3 |
4.0.0 |
Added the following:
- Added Available Reconfiguration groups Using FHT Transceivers table in Supported Reconfiguration Groups.
- Added Timestamp Accuracy Support for FHT Transceivers in PTP Timestamp Accuracy Support.
Added the following in Interface Overview section:
- Added i_clk_pll input clock signals in Clock Signals section.
- Updated the description for reset signals i_p0_rst_n in Reset Signals.
- Supported Timestamp Accuracy Modes per Profile table for FHT reconfiguration groups in PTP Clock Interface.
- Fractured MAC Segmented Interface for FHT Transceivers in Interface Overview.
- Fractured MAC Avalon ST Client Interface for FHT Transceivers in Interface Overview.
- Fractured MII PCS-Only Interface for FHT Transceivers Interface Overview.
- Fractured PCS66 Interface for OTN/FlexE for FHT Transceivers in Interface Overview.
- Signals of the Precision Time Protocol (PTP) Interface in Precision Time Protocol Interface.
- Signals of the Time-of-Day (TOD) Interface for FHT Reconfiguration Groups in Time-of-Day Interface.
- Added FHT Reconfiguration Groups to signals of the PTP Status Interface table in PTP Status Interface.
Added the following in Parameters section.
- FHT supports 50G-100G per lane.
- Ready Latency parameter.
- Enable TX Packing Parameter.
- Enable asynchronous adapter clocks Parameter.
- FHT startup profiles under Startup Profile Options.
- Updated IP parameter Editor: IP tab image in Parameters.
- Added Configure Reference Clock for FHT PMA in Reference ans System PLL Clock for your IP Design.
Added the following in Configuration Registers section.
- Signal decoding for the FHT transceivers
- Port-specific bit definitions for 0x208 offset.
Added Document Archive section. |
| 2022.06.20 |
22.2 |
3.0.0 |
Added the following:
- Footnote in parameters setting-IP tab table under PTP options.
- The number of allowed ports-PTP GUI options table in Parameters section.
- PTP Clock Interface topic in PTP interface.
- Supported Timestamp Accuracy Modes per Profile table in PTP Clock Interface.
- Compilation note F-tile Ethernet Multirate IP automatically generates the F-tile PTP adapter in PTP Tile Interface.
- Limitations of PTP in F-Tile Ethernet Multirate IP Core Features and Constraints.
- Added new topic Fractured MAC SOP-Aligned Client Interface for FGT Transceivers in Interface Overview.
- Updated note in Device Speed Grade Support.
- Updated PTP Status Interface table in PTP Interface.
- Updated Release Information in Introduction section.
- Updated i_reconfig_clk description in Clock Signals table:
- When PTP is enabled, the i_reconfig_clk frequency supports the range of 100 to 250 MHz.
|
| 2022.04.04 |
22.1 |
2.0.0 |
Initial release. |