F-Tile Ethernet Multirate Intel® FPGA IP User Guide

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ID 714307
Date 5/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile Ethernet Multirate Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide
1. Introduction x
1.1. Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation 1.7. F-Tile Ethernet Multirate IP Core Features and Constraints 1.8. F-Tile Ethernet Multirate IP Core Concepts
1.8. F-Tile Ethernet Multirate IP Core Concepts x
1.8.1. Reconfiguration Group 1.8.2. Base Profile 1.8.3. Secondary Profile 1.8.4. Secondary Profile Group 1.8.5. Startup Profile 1.8.6. Supported Reconfiguration Groups 1.8.7. PTP Timestamp Accuracy Support 1.8.8. Transceiver Lane Mapping
2. Interface Overview x
2.1. Port Numbering Scheme 2.2. Clock Signals 2.3. Reset Signals 2.4. Fractured MAC Segmented Interface for FGT Transceivers 2.5. Fractured MAC Segmented Interface for FHT Transceivers 2.6. Fractured MAC Avalon ST Client Interface for FGT Transceivers 2.7. Fractured MAC Avalon ST Client Interface for FHT Transceivers 2.8. Fractured MII PCS-Only Interface for FGT Transceivers 2.9. Fractured MII PCS-Only Interface for FHT Transceivers 2.10. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers 2.11. Fractured PCS66 Interface for OTN/FlexE for FHT Transceivers 2.12. MAC Flow Control Interface 2.13. Status Interface 2.14. Avalon® Memory-Mapped Reconfiguration Interfaces 2.15. Auto-Negotiation and Link Training Interface 2.16. Precision Time Protocol Interface
2.16. Precision Time Protocol Interface x
2.16.1. PTP Clock Interface 2.16.2. Time-of-Day Interface 2.16.3. TX 2-Step Timestamp Interface 2.16.4. TX 1-Step Timestamp Interface 2.16.5. RX Timestamp Interface 2.16.6. PTP Status Interface 2.16.7. PTP Tile Interface
4. Designing with the IP Core x
4.1. Specifying the IP Core Parameters and Options 4.2. Generated File Structure
4.1. Specifying the IP Core Parameters and Options x
4.1.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Precision Time Protocol
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Ethernet Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide

2.6. Fractured MAC Avalon ST Client Interface for FGT Transceivers

This section describes the fractured interface signals when you select the MAC Avalon ST client interface in the IP parameter editor.

The datapath interface consists of a fractured interface where the same set of signals is re-used for a single or multiple port datapath connections.

The following tables displays the ports details and the supported variants for each of the reconfiguration groups. The mode selection refers to the Ethernet mode parameter in the F-Tile Ethernet Multirate IP core Profile # IP Configuration tab.

Table 29.  Fractured MAC Avalon ST Client Interface Signals for 25GE-1 Reconfigurable GroupFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Top Level Interface Mode TX Interface RX Interface

i_tx_data[63:0]

i_tx_valid

i_tx_startofpacket

i_tx_endofpacket

i_tx_empty[2:0]

0_tx_avst_ready

i_tx_error

i_tx_skip_crc

o_rx_data[63:0]

o_rx_valid

o_rx_startofpacket

0_rx_endofpacket

o_rx_empty[2:0]

o_rx_error[5:0]

o_rxstatus_data[39:0]

o_rxstatus_valid

1x 10GE-1/

1x 25G-1

Port 0:

i_tx_data[63:0]

i_tx_valid

i_tx_startofpacket

i_tx_endofpacket

o_tx_ready

i_tx_error

i_tx_skip_crc

Port 0:

o_rx_data[63:0]

o_rx_valid

o_rx_startofpacket

o_rx_endofpacket

o_rx_empty[2:0]

o_rx_error[5:0]

o_rxstatus_data[39:0]

o_rxstatus_valid

Table 30.  Fractured MAC Avalon ST Client Interface Signals for 50GE-1 Reconfigurable GroupFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Top Level Interface Mode TX Interface RX Interface

i_tx_data[127:0]

i_tx_valid

i_tx_startofpacket

i_tx_endofpacket

i_tx_empty[5:0]

o_tx_ready

i_tx_preamble[63:0]

i_tx_error

i_tx_skip_crc

o_rx_data[127:0]

o_rx_valid

o_rx_startofpacket

o_rx_endofpacket

o_rx_empty[5:0]

o_rx_error[5:0]

o_rxstatus_data[39:0]

o_rxstatus_valid

o_rx_preamble[63:0] 4

1x 10GE-1/

1x 25GE-1

Port 0:

i_tx_data[63:0]

i_tx_valid

i_tx_startofpacket

i_tx_endofpacket

i_tx_empty[2:0]

o_tx_ready

i_tx_error

i_tx_skip_crc

Port 0:

o_rx_data[63:0]

o_rx_valid

o_rx_startofpacket]

o_rx_endofpacket

o_rx_empty[2:0]

o_rx_error[5:0]

o_rxstatus_data[39:0]

o_rxstatus_valid

1x 50GE-1

Port 0:

i_tx_data[127:0]

i_tx_valid

i_tx_startofpacket

i_tx_endofpacket

i_tx_empty[3:0]

o_tx_ready

i_tx_preamble[63:0]

i_tx_error

i_tx_skip_crc

Port 0:

o_rx_data[127:0]

o_rx_valid

o_rx_startofpacket

o_rx_endofpacket

o_rx_empty[4:0]

o_rx_error[5:0]

o_rxstatus_data[39:0]

o_rxstatus_valid

o_rx_preamble[63:0] 4

Table 31.  Fractured Avalon ST Client Interface Signals for 100GE-4 Reconfigurable GroupFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Top Level Interface Mode TX Interface RX Interface

i_tx_data[511:0]

i_tx_valid[3:0]

i_tx_startofpacket[3:0]

i_tx_endofpacket[3:0]

i_tx_empty[11:0]

o_tx_ready[3:0]

i_tx_preamble[127:0]

i_tx_error[3:0]

i_tx_skip_crc[3:0]

o_rx_data[511:0]

o_rx_valid[3:0]

o_rx_startofpacket[3:0]

o_rx_endofpacket[3:0]

o_rx_empty[11:0]

o_rx_error[23:0]

o_rxstatus_data[159:0]

o_rxstatus_valid[3:0]

o_rx_preamble[127:0]

4x10GE-1/

4x 25GE-1

Port 0:

i_tx_data[63:0]

i_tx_valid[0]

i_tx_startofpacket[0]

i_tx_endofpacket[0]

i_tx_empty[2:0]

o_tx_ready[0]

i_tx_error[0]

i_tx_skip_crc[0]

Port 1:

i_tx_data[127:64]

i_tx_valid[1]

i_tx_startofpacket[1]

i_tx_endofpacket[1]

i_tx_empty[5:3]

o_tx_ready[1]

i_tx_error[1]

i_tx_skip_crc[1]

Port 2:

i_tx_data[191:128]

i_tx_valid[2]

i_tx_startofpacket[2]

i_tx_endofpacket[2]

i_tx_empty[8:6]

o_tx_ready[2]

i_tx_error[2]

i_tx_skip_crc[2]

Port 3:

i_tx_data[255:192]

i_tx_valid[3]

i_tx_startofpacket[3]

i_tx_endofpacket[3]

i_tx_empty[11:9]

o_tx_ready[3]

i_tx_error[3]

i_tx_skip_crc[3]

Port 0:

o_rx_data[63:0]

o_rx_valid[0]

o_rx_startofpacket[0]

o_rx_endofpacket[0]

o_rx_empty[2:0]

o_rx_error[5:0]

o_rxstatus_data[39:0]

o_rxstatus_valid[0]

Port 1:

o_rx_data[127:64]

o_rx_valid[1]

o_rx_startofpacket[1]

o_rx_endofpacket[1]

o_rx_empty[5:3]

o_rx_error[11:6]

o_rxstatus_data[79:40]

o_rxstatus_valid[1]

Port 2:

o_rx_data[191:128]

o_rx_valid[2]

o_rx_startofpacket[2]

o_rx_endofpacket[2]

o_rx_empty[8:6]

o_rx_error[17:12]

o_rxstatus_data[119:80]

o_rxstatus_valid[2]

Port 3:

o_rx_data[255:192]

o_rx_valid[3]

o_rx_startofpacket[3]

o_rx_endofpacket[3]

o_rx_empty[11:9]

o_rx_error[23:18]

o_rxstatus_data[159:120]

o_rxstatus_valid[3]

2x 50GE-2/

2x 50GE-1

Port 0:

i_tx_data[127:0]

i_tx_valid[0]

i_tx_startofpacket[0]

i_tx_endofpacket[0]

i_tx_empty[3:0]

o_tx_ready[0]

i_tx_preamble[63:0]

i_tx_error[0]

i_tx_skip_crc[0]

Port 2:

i_tx_data[255:128]

i_tx_valid[2]

i_tx_startofpacket[2]

i_tx_endofpacket[2]

i_tx_empty[7:4]

o_tx_ready[2]

i_tx_preamble[127:64]

i_tx_error[2]

i_tx_skip_crc[2]

Port 0:

o_rx_data[127:0]

o_rx_valid[0]

o_rx_startofpacket[0]

o_rx_endofpacket[0]

o_rx_empty[3:0]

o_rx_error[5:0]

o_rxstatus_data[39:0]

o_rxstatus_valid[0]

o_rx_preamble[63:0]

Port 2:

o_rx_data[255:128]

o_rx_valid[2]

o_rx_startofpacket[2]

o_rx_endofpacket[2]

o_rx_empty[7:4]

o_rx_error[17:12]

o_rxstatus_data[119:80]

o_rxstatus_valid[2]

o_rx_preamble[127:64]

1x 40GE-4

Port 0:

i_tx_data[127:0]

i_tx_valid[0]

i_tx_startofpacket[0]

i_tx_endofpacket[0]

i_tx_empty[3:0]

o_tx_ready[0]

i_tx_preamble[63:0]

i_tx_error[0]

i_tx_skip_crc[0]

Port 0:

o_rx_data[127:0]

o_rx_valid[0]

o_rx_startofpacket[0]

o_rx_endofpacket[0]

o_rx_empty[3:0]

o_rx_error[5:0]

o_rxstatus_data[39:0]

o_rxstatus_valid[0]

o_rx_preamble[63:0]

1x 100GE-4/

1x 100GE-2

Port 0:

i_tx_data[511:0]

i_tx_valid[0]

i_tx_startofpacket[0]

i_tx_endofpacket[0]

i_tx_empty[5:0]

o_tx_ready[0]

i_tx_error[0]

i_tx_skip_crc[0]

Port 0:

o_rx_data[511:0]

o_rx_valid[0]

o_rx_startofpacket[0]

o_rx_endofpacket[0]

o_rx_empty[5:0]

o_rx_error[5:0]

o_rxstatus_data[39:0]

o_rxstatus_valid[0]

Table 32.  Fractured Avalon ST Client Interface Signal for 100GE-2 Reconfigurable GroupFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Top Level Interface Mode TX Interface RX Interface

i_tx_data[511:0]

i_tx_valid[1:0]

i_tx_startofpacket[1:0]

i_tx_endofpacket[1:0]

i_tx_empty[11:0]

o_tx_ready[1:0]

i_tx_preamble[127:0]

i_tx_error[1:0]

i_tx_skip_crc[1:0]

o_rx_data[511:0]

o_rx_valid[1:0]

o_rx_startofpacket[1:0]

o_rx_endofpacket[1:0]

o_rx_empty[11:0]

o_rx_error[11:0]

o_rxstatus_data[79:0]

o_rxstatus_valid[1:0]

o_rx_preamble[127:0]

1x 100GE-2

Port 0:

i_tx_data[511:0]

i_tx_valid[0]

i_tx_startofpacket[0]

i_tx_endofpacket[0]

i_tx_empty[5:0]

o_tx_ready[0]

i_tx_error[0]

i_tx_skip_crc[0]

Port 0:

o_rx_data[511:0]

o_rx_valid[0]

o_rx_startofpacket[0]

o_rx_endofpacket[0]

o_rx_empty[5:0]

o_rx_error[5:0]

o_rxstatus_data[39:0]

o_rxstatus_valid[0]

2x 50GE-1

Port 0:

i_tx_data[127:0]

i_tx_valid[0]

i_tx_startofpacket[0]

i_tx_endofpacket[0]

i_tx_empty[3:0]

o_tx_ready[0]

i_tx_preamble[63:0]

i_tx_error[0]

i_tx_skip_crc[0]

Port 1:

i_tx_data[255:128]

i_tx_valid[1]

i_tx_startofpacket[1]

i_tx_endofpacket[1]

i_tx_empty[7:4]

o_tx_ready[1]

i_tx_preamble[127:64]

i_tx_error[1]

i_tx_skip_crc[1]

Port 0:

o_rx_data[127:0]

o_rx_valid[0]

o_rx_startofpacket[0]

o_rx_endofpacket[0]

o_rx_empty[3:0]

o_rx_error[5:0]

o_rxstatus_data[39:0]

o_rxstatus_valid[0]

o_rx_preamble[63:0]

Port 1:

o_rx_data[255:128]

o_rx_valid[1]

o_rx_startofpacket[1]

o_rx_endofpacket[1]

o_rx_empty[7:4]

o_rx_error[11:6]

o_rxstatus_data[79:40]

o_rxstatus_valid[1]

o_rx_preamble[127:64]

2x 25GE-1/

2x 10GE-1

Port 0:

i_tx_data[63:0]

i_tx_valid[0]

i_tx_startofpacket[0]

i_tx_endofpacket[0]

i_tx_empty[2:0]

o_tx_ready[0]

i_tx_error[0]

i_tx_skip_crc[0]

Port 1:

i_tx_data[127:64]

i_tx_valid[1]

i_tx_startofpacket[1]

i_tx_endofpacket[1]

i_tx_empty[5:3]

o_tx_ready[1]

i_tx_error[1]

i_tx_skip_crc[1]

Port 0:

o_rx_data[63:0]

o_rx_valid[0]

o_rx_startofpacket[0]

o_rx_endofpacket[0]

o_rx_empty[2:0]

o_rx_error[5:0]

o_rxstatus_data[39:0]

o_rxstatus_valid[0]

Port 1:

o_rx_data[127:64]

o_rx_valid[1]

o_rx_startofpacket[1]

o_rx_endofpacket[1]

o_rx_empty[5:3]

o_rx_error[11:6]

o_rxstatus_data[79:40]

o_rxstatus_valid[1]

1x 50GE-2

Port 0:

i_tx_data[127:0]

i_tx_valid[0]

i_tx_startofpacket[0]

i_tx_endofpacket[0]

i_tx_empty[3:0]

o_tx_ready[0]

i_tx_preamble[63:0]

i_tx_error[0]

i_tx_skip_crc[0]

Port 0:

o_rx_data[127:0]

o_rx_valid[0]

o_rx_startofpacket[0]

o_rx_endofpacket[0]

o_rx_empty[3:0]

o_rx_error[5:0]

o_rxstatus_data[39:0]

o_rxstatus_valid[0]

o_rx_preamble[63:0]

4 These signals are only applicable when Enable Preamble passthrough is selection in the IP parameter.
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