Visible to Intel only — GUID: pzl1653697016689
Ixiasoft
Visible to Intel only — GUID: pzl1653697016689
Ixiasoft
2.16.1. PTP Clock Interface
A separate time-of-day (TOD) clock interface is available for each port within a reconfiguration group. Every clock port in a reconfiguration group must be driven regardless of the number of active ports being used.
The IP core supports two timestamps accuracy modes, Basic and Advanced. In advanced mode, additional logic generates the high accuracy PTP timestamps.
PTP Timestamp Accuracy in Basic Mode
When you select Basic in the Timestamp accuracy mode under PTP tab in the parameter editor for F-Tile Ethernet Multirate IP core, TX and RX data paths of multiple Ethernet IP instances share a single TOD clock output. The time-of-day (TOD) module can be shared across multiple IP instances of different data rates.
PTP Timestamp Accuracy in Advanced Mode
When you select Advanced in the Timestamp accuracy mode under PTP tab in the parameter editor, the IP core requires a dedicated TOD modules for both, TX and RX data path of each port.
- TX transceiver reference clocks of each port are shared, or from the source with the same clock frequency PPM.
- TX transceiver channel that output the clock driving the shared TOD must not reset after the TX_div clock is stable.
- While other ports are active, the IP does not allow dynamic reconfiguration to the port output that shared TX_div clock. A dynamic reconfiguration of all ports together is allowed.
- All ports operate at the same Ethernet rate.
If you need to dynamically reconfigure your design to support 10GB Ethernet with PTP in Advanced Accuracy Mode, Intel® recommends the following TOD connection.
A single instance of TOD Synchronizer can only support a single synchronization mode, therefore a dedicated TOD module is needed for each rate in TX and RX PTP data path of each port. You must correctly configure the TOD multiplexer according to the current operating state.
- TX transceiver reference clocks of each port are shared, or from the source with the same clock frequency PPM
- TX transceiver channel that output the clock driving the shared TOD must not reset after the TX_div clock is stable
- While other ports are active, the IP does not allow dynamic reconfiguration to the port output that shared TX_div clock. A dynamic reconfiguration of all ports together is allowed.
- All ports operate at the same Ethernet rate