F-Tile Ethernet Multirate Intel® FPGA IP User Guide

ID 714307
Date 5/01/2024
Public
Document Table of Contents

2.13. Status Interface

The status interface is available for each supported port within a reconfiguration group.
The table displays the interface signals for different numbers of ports.
Table 64.  Signals of the Status Interface SignalsFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Number of Ports Signal Name
1 Port 0:

o_p0_rx_block_lock

o_p0_rx_am_lock

o_p0_local_fault_status

o_p0_remote_fault_status

i_p0_stats_snapshot

o_p0_rx_hi_ber

o_p0_rx_pcs_fully_aligned

2 Port 0:

o_p0_rx_block_lock

o_p0_rx_am_lock

o_p0_local_fault_status

o_p0_remote_fault_status

i_p0_stats_snapshot

o_p0_rx_hi_ber

o_p0_rx_pcs_fully_aligned

Port 1:

o_p1_rx_block_lock

o_p1_rx_am_lock

o_p1_local_fault_status

o_p1_remote_fault_status

i_p1_stats_snapshot

o_p1_rx_hi_ber

o_p1_rx_pcs_fully_aligned

4 Port 0:

o_p0_rx_block_lock

o_p0_rx_am_lock

o_p0_local_fault_status

o_p0_remote_fault_status

i_p0_stats_snapshot

o_p0_rx_hi_ber

o_p0_rx_pcs_fully_aligned

Port 1:

o_p1_rx_block_lock

o_p1_rx_am_lock

o_p1_local_fault_status

o_p1_remote_fault_status

i_p1_stats_snapshot

o_p1_rx_hi_ber

o_p1_rx_pcs_fully_aligned

Port 2:

o_p2_rx_block_lock

o_p2_rx_am_lock

o_p2_local_fault_status

o_p2_remote_fault_status

i_p2_stats_snapshot

o_p2_rx_hi_ber

o_p2_rx_pcs_fully_aligned

Port 3:

o_p3_rx_block_lock

o_p3_rx_am_lock

o_p3_local_fault_status

o_p3_remote_fault_status

i_p3_stats_snapshot

o_p3_rx_hi_ber

o_p3_rx_pcs_fully_aligned