F-Tile Ethernet Multirate Intel® FPGA IP User Guide

Download PDF
ID 714307
Date 5/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile Ethernet Multirate Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide
1. Introduction x
1.1. Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation 1.7. F-Tile Ethernet Multirate IP Core Features and Constraints 1.8. F-Tile Ethernet Multirate IP Core Concepts
1.8. F-Tile Ethernet Multirate IP Core Concepts x
1.8.1. Reconfiguration Group 1.8.2. Base Profile 1.8.3. Secondary Profile 1.8.4. Secondary Profile Group 1.8.5. Startup Profile 1.8.6. Supported Reconfiguration Groups 1.8.7. PTP Timestamp Accuracy Support 1.8.8. Transceiver Lane Mapping
2. Interface Overview x
2.1. Port Numbering Scheme 2.2. Clock Signals 2.3. Reset Signals 2.4. Fractured MAC Segmented Interface for FGT Transceivers 2.5. Fractured MAC Segmented Interface for FHT Transceivers 2.6. Fractured MAC Avalon ST Client Interface for FGT Transceivers 2.7. Fractured MAC Avalon ST Client Interface for FHT Transceivers 2.8. Fractured MII PCS-Only Interface for FGT Transceivers 2.9. Fractured MII PCS-Only Interface for FHT Transceivers 2.10. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers 2.11. Fractured PCS66 Interface for OTN/FlexE for FHT Transceivers 2.12. MAC Flow Control Interface 2.13. Status Interface 2.14. Avalon® Memory-Mapped Reconfiguration Interfaces 2.15. Auto-Negotiation and Link Training Interface 2.16. Precision Time Protocol Interface
2.16. Precision Time Protocol Interface x
2.16.1. PTP Clock Interface 2.16.2. Time-of-Day Interface 2.16.3. TX 2-Step Timestamp Interface 2.16.4. TX 1-Step Timestamp Interface 2.16.5. RX Timestamp Interface 2.16.6. PTP Status Interface 2.16.7. PTP Tile Interface
4. Designing with the IP Core x
4.1. Specifying the IP Core Parameters and Options 4.2. Generated File Structure
4.1. Specifying the IP Core Parameters and Options x
4.1.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Precision Time Protocol
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Ethernet Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide

2.1. Port Numbering Scheme

Some reconfiguration groups support multiple numbers of ports. The number of supported ports within each group can be 1, 2, or 4.
Note: All the ports supported in a profile share the datapath interface. Therefore, the datapath interface name convention does not include the port numbering. Nevertheless, all other port-specific signals contain a port number in their name to ease customer usability.
Table 11.  Active Ports Numbering in a Multiple Port Profile
Maximum Number of Ports Active Ports Port Numbering Applicable Profiles Applicable Reconfiguration Groups
4 1 0

1x 100GE-4

1x 40GE-4

1x 100GE-2

1x 400GE-8

1x 200GE-4
  • 100GE-4 Reconfigurable
  • 400GE-8 Reconfigurable
  • 200GE-4 Reconfigurable
2 0, 2

2x 50GE-1

2x 50GE-2

2x 200GE-4

2x 100GE-2
4 0, 1, 2, 3

4x 25GE-1

4x 10GE-1

4x 100GE-2

4x 50GE-1
2 1 0

1x 100GE-2

1x 50GE-2

1x 200GE-2
  • 100GE-2 Reconfigurable
2 0,1

2x 100GE-1

2x 100GE-2

2x 50GE-1

2x 10GE-1

2x 25GE-1
1 1 0

1x 10GE-1

1x 25GE-1

1x 50GE-1

1x 100GE-1
  • 25GE-1 Reconfigurable
  • 50GE-1 Reconfigurable
Level Two Title