F-Tile Ethernet Multirate Intel® FPGA IP User Guide

ID 714307
Date 5/01/2024
Public
Document Table of Contents

2.10. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers

This section describes the fractured interface signals when you select the PCS66 OTN or PCS66 FlexE client interface in the IP parameter editor.

The datapath interface consists of a fractured interface where the same set of signals is re-used for a single or multiple port datapath connections.

The following tables displays the ports details and the supported variants for each of the reconfiguration groups. The mode selection refers to the Ethernet mode parameter in the F-Tile Ethernet Multirate IP core Profile # IP Configuration tab.

Table 50.  Signals of the Fractured PCS66 Interface for OTN/FlexE for 25GE-1 Reconfigurable GroupFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Top Level Interface Mode TX Interface RX Interface

i_tx_pcs66_d[65:0]

i_tx_pcs66_valid

i_tx_pcs66_am

o_tx_pcs66_ready

o_rx_pcs66_d[65:0]

o_rx_pcs66_valid

o_rx_pcs66_am_valid

1x 25GE-1/

1x 10GE-1

Port 0:

i_tx_pcs66_d[65:0]

i_tx_pcs66_valid

i_tx_pcs66_am

o_tx_pcs66_ready

Port 0:

o_rx_pcs66_d[65:0]

o_rx_pcs66_valid

o_rx_pcs66_am_valid

Table 51.  Signals of the Fractured PCS66 Interface for OTN/FlexE for 50GE-1 Reconfigurable GroupFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Top Level Interface Mode TX Interface RX Interface

i_tx_pcs66_d[131:0]

i_tx_pcs66_valid

i_tx_pcs66_am

o_tx_pcs66_ready

o_rx_pcs66_d[131:0]

o_rx_pcs66_valid

o_rx_pcs66_am_valid

1x 25GE-1/

1x 10GE-1

Port 0:

i_tx_pcs66_d[65:0]

i_tx_pcs66_valid

i_tx_pcs66_am

o_tx_pcs66_ready

Port 0:

o_rx_pcs66_d[65:0]

o_rx_pcs66_valid

o_rx_pcs66_am_valid

1x 50GE-1

Port 0:

i_tx_pcs66_d[131:0]

i_tx_pcs66_valid

i_tx_pcs66_am

o_tx_pcs66_ready

Port 0:

o_rx_pcs66_d[131:0]

o_rx_pcs66_valid

o_rx_pcs66_am_valid

Table 52.  Signals of the Fractured PCS66 Interface for OTN/FlexE for 100GE-4 Reconfigurable GroupFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Top Level Interface Mode TX Interface RX Interface

i_tx_pcs66_d[263:0]

i_tx_pcs66_valid[3:0]

i_tx_pcs66_am[3:0]

o_tx_pcs66_ready[3:0]

o_rx_pcs66_d[263:0]

o_rx_pcs66_valid[3:0]

o_rx_pcs66_am_valid[3:0]

4x 25GE-1/

4x 10GE-1

Port 0:

i_tx_pcs66_d[65:0]

i_tx_pcs66_valid[0]

i_tx_pcs66_am[0]

o_tx_pcs66_ready[0]

Port 1:

i_tx_pcs66_d[131:66]

i_tx_pcs66_valid[1]

i_tx_pcs66_am[1]

o_tx_pcs66_ready[1]

Port 2:

i_tx_pcs66_d[197:132]

i_tx_pcs66_valid[2]

i_tx_pcs66_am[2]

o_tx_pcs66_ready[2]

Port 3:

i_tx_pcs66_d[263:198]

i_tx_pcs66_valid[3]

i_tx_pcs66_am[3]

o_tx_pcs66_ready[3]

Port 0:

o_rx_pcs66_d[65:0]

o_rx_pcs66_valid[0]

o_rx_pcs66_am_valid[0]

Port 1:

o_rx_pcs66_d[131:66]

o_rx_pcs66_valid[1]

o_rx_pcs66_am_valid[1]

Port 2:

o_rx_pcs66_d[197:132]

o_rx_pcs66_valid[2]

o_rx_pcs66_am_valid[2]

Port 3:

o_rx_pcs66_d[263:198]

o_rx_pcs66_valid[3]

o_rx_pcs66_am_valid[3]

2x 50GE-2/

2x 50GE-1

Port 0:

i_tx_pcs66_d[131:0]

i_tx_pcs66_valid[0]

i_tx_pcs66_am[0]

o_tx_pcs66_ready[0]

Port 2:

i_tx_pcs66_d[263:132]

i_tx_pcs66_valid[2]

i_tx_pcs66_am[2]

o_tx_pcs66_ready[2]

Port 0:

o_rx_pcs66_d[131:0]

o_rx_pcs66_valid[0]

o_rx_pcs66_am_valid[0]

Port 2:

o_rx_pcs66_d[263:132]

o_rx_pcs66_valid[2]

o_rx_pcs66_am_valid[2]

1x 100GE-4/

1x 100GE-2

Port 0:

i_tx_pcs66_d[263:0]

i_tx_pcs66_valid[0]

i_tx_pcs66_am[0]

o_tx_pcs66_ready[0]

Port 0:

o_rx_pcs66_d[263:0]

o_rx_pcs66_valid[0]

o_rx_pcs66_am_valid[0]

Table 53.  Signals of the Fractured PCS66 Interface for OTN/FlexE for 100GE-2 Reconfigurable GroupFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Top Level Interface Mode TX Interface RX Interface

i_tx_pcs66_d[263:0]

i_tx_pcs66_valid[1:0]

i_tx_pcs66_am[1:0]

o_tx_pcs66_ready[1:0]

o_rx_pcs66_d[263:0]

o_rx_pcs66_valid[1:0]

o_rx_pcs66_am_valid[1:0]

1x 100GE-2

Port 0:

i_tx_pcs66_d[263:0]

i_tx_pcs66_valid[0]

i_tx_pcs66_am[0]

o_tx_pcs66_ready[0]

Port 0:

o_rx_pcs66_d[263:0]

o_rx_pcs66_valid[0]

o_rx_pcs66_am_valid[0]

2x 50GE-1

Port 0:

i_tx_pcs66_d[131:0]

i_tx_pcs66_valid[0]

i_tx_pcs66_am[0]

o_tx_pcs66_ready[0]

Port 1:

i_tx_pcs66_d[263:132]

i_tx_pcs66_valid[1]

i_tx_pcs66_am[1]

o_tx_pcs66_ready[1]

Port 0:

o_rx_pcs66_d[131:0]

o_rx_pcs66_valid[0]

o_rx_pcs66_am_valid[0]

Port 1:

o_rx_pcs66_d[263:132]

o_rx_pcs66_valid[1]

o_rx_pcs66_am_valid[1]

2x 25GE-1/

2x 10GE-1

Port 0:

i_tx_pcs66_d[65:0]

i_tx_pcs66_valid[0]

i_tx_pcs66_am[0]

o_tx_pcs66_ready[0]

Port 1:

i_tx_pcs66_d[197:132]

i_tx_pcs66_valid[1]

i_tx_pcs66_am[1]

o_tx_pcs66_ready[1]

Port 0:

o_rx_pcs66_d[65:0]

o_rx_pcs66_valid[0]

o_rx_pcs66_am_valid[0]

Port 1:

o_rx_pcs66_d[197:132]

o_rx_pcs66_valid[1]

o_rx_pcs66_am_valid[1]

1x 50GE-2

Port 0:

i_tx_pcs66_d[131:0]

i_tx_pcs66_valid[0]

i_tx_pcs66_am[0]

o_tx_pcs66_ready[0]

Port 0:

o_tx_pcs66_d[131:0]

o_tx_pcs66_valid[0]

o_tx_pcs66_am_valid[0]

Table 54.  Signals of the Fractured PCS66 Interface for OTN/FlexE for 400GE-8 Reconfigurable GroupFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Top Level Interface Mode TX Interface RX Interface

i_tx_pcs66_d[1055:0]

i_tx_pcs66_valid[3:0]

i_tx_pcs66_am[3:0]

o_tx_pcs66_ready[3:0]

o_rx_pcs66_d[1055:0]

o_rx_pcs66_valid[3:0]

o_rx_pcs66_am_valid[3:0]

1x 400GE-8

Port 0:

i_tx_pcs66_d[1055:0]

i_tx_pcs66_valid[0]

i_tx_pcs66_am[0]

o_tx_pcs66_ready[0]

Port 0:

o_tx_pcs66_d[1055:0]

o_tx_pcs66_valid[0]

o_tx_pcs66_am_valid[0]

2x 200GE-4

Port 0:

i_tx_pcs66_d[527:0]

i_tx_pcs66_valid[0]

i_tx_pcs66_am[0]

o_tx_pcs66_ready[0]

Port 2:

i_tx_pcs66_d[1055:528]

i_tx_pcs66_valid[2]

i_tx_pcs66_am[2]

o_tx_pcs66_ready[2]

Port 0:

o_rx_pcs66_d[527:0]

o_rx_pcs66_valid[0]

o_rx_pcs66_am_valid[0]

Port 2:

o_rx_pcs66_d[1055:528]

o_rx_pcs66_valid[2]

o_rx_pcs66_am_valid[2]

4x 100GE-2

Port 0:

i_tx_pcs66_d[263:0]

i_tx_pcs66_valid[0]

i_tx_pcs66_am[0]

o_tx_pcs66_ready[0]

Port 1:

i_tx_pcs66_d[527:264]

i_tx_pcs66_valid[1]

i_tx_pcs66_am[1]

o_tx_pcs66_ready[1]

Port 2:

i_tx_pcs66_d[791:528]

i_tx_pcs66_valid[2]

i_tx_pcs66_am[2]

o_tx_pcs66_ready[2]

Port 3:

i_tx_pcs66_d[1055:792]

i_tx_pcs66_valid[3]

i_tx_pcs66_am[3]

o_tx_pcs66_ready[3]

Port 0:

o_rx_pcs66_d[263:0]

o_rx_pcs66_valid[0]

o_rx_pcs66_am_valid[0]

Port 1:

o_rx_pcs66_d[527:264]

o_rx_pcs66_valid[1]

o_rx_pcs66_am_valid[1]

Port 2:

o_rx_pcs66_d[791:528]

o_rx_pcs66_valid[2]

o_rx_pcs66_am_valid[2]

Port 3:

o_rx_pcs66_d[1055:792]

o_rx_pcs66_valid[3]

o_rx_pcs66_am_valid[3]

Table 55.  Signals of the Fractured PCS66 Interface for OTN/FlexE for 200GE-4 Reconfigurable GroupFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Top Level Interface Mode TX Interface RX Interface

i_tx_pcs66_d[527:0]

i_tx_pcs66_valid[3:0]

i_tx_pcs66_am[3:0]

o_tx_pcs66_ready[3:0]

o_rx_pcs66_d[527:0]

o_rx_pcs66_valid[3:0]

o_rx_pcs66_am_valid[3:0]

1x 200GE-4

Port 0:

i_tx_pcs66_d[527:0]

i_tx_pcs66_valid[0]

i_tx_pcs66_am[0]

o_tx_pcs66_ready[0]

Port 0:

o_tx_pcs66_d[527:0]

o_tx_pcs66_valid[0]

o_tx_pcs66_am_valid[0]

2x 100GE-2

Port 0:

i_tx_pcs66_d[263:0]

i_tx_pcs66_valid[0]

i_tx_pcs66_am[0]

o_tx_pcs66_ready[0]

Port 2:

i_tx_pcs66_d[527:264]

i_tx_pcs66_valid[2]

i_tx_pcs66_am[2]

o_tx_pcs66_ready[2]

Port 0:

o_rx_pcs66_d[263:0]

o_rx_pcs66_valid[0]

o_rx_pcs66_am_valid[0]

Port 2:

o_rx_pcs66_d[527:264]

o_rx_pcs66_valid[2]

o_rx_pcs66_am_valid[2]

4x 50GE-1

Port 0:

i_tx_pcs66_d[131:0]

i_tx_pcs66_valid[0]

i_tx_pcs66_am[0]

o_tx_pcs66_ready[0]

Port 1:

i_tx_pcs66_d[263:132]

i_tx_pcs66_valid[1]

i_tx_pcs66_am[1]

o_tx_pcs66_ready[1]

Port 2:

i_tx_pcs66_d[395:264]

i_tx_pcs66_valid[2]

i_tx_pcs66_am[2]

o_tx_pcs66_ready[2]

Port 3:

i_tx_pcs66_d[527:396]

i_tx_pcs66_valid[3]

i_tx_pcs66_am[3]

o_tx_pcs66_ready[3]

Port 0:

o_rx_pcs66_d[131:0]

o_rx_pcs66_valid[0]

o_rx_pcs66_am_valid[0]

Port 1:

o_rx_pcs66_d[263:132]

o_rx_pcs66_valid[1]

o_rx_pcs66_am_valid[1]

Port 2:

o_rx_pcs66_d[395:264]

o_rx_pcs66_valid[2]

o_rx_pcs66_am_valid[2]

Port 3:

o_rx_pcs66_d[527:396]

o_rx_pcs66_valid[3]

o_rx_pcs66_am_valid[3]

2x 50GE-2

Port 0:

i_tx_pcs66_d[131:0]

i_tx_pcs66_valid[0]

i_tx_pcs66_am[0]

o_tx_pcs66_ready[0]

Port 2:

i_tx_pcs66_d[395:264]

i_tx_pcs66_valid[2]

i_tx_pcs66_am[2]

o_tx_pcs66_ready[2]

Port 0:

o_rx_pcs66_d[131:0]

o_rx_pcs66_valid[0]

o_rx_pcs66_am_valid[0]

Port 2:

o_rx_pcs66_d[395:264]

o_rx_pcs66_valid[2]

o_rx_pcs66_am_valid[2]

1x 100GE-4

Port 0:

i_tx_pcs66_d[263:0]

i_tx_pcs66_valid[0]

i_tx_pcs66_am[0]

o_tx_pcs66_ready[0]

Port 0:

o_tx_pcs66_d[263:0]

o_tx_pcs66_valid[0]

o_tx_pcs66_am_valid[0]