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2.1. Port Numbering Scheme
2.2. Clock Signals
2.3. Reset Signals
2.4. Fractured MAC Segmented Interface for FGT Transceivers
2.5. Fractured MAC Segmented Interface for FHT Transceivers
2.6. Fractured MAC Avalon ST Client Interface for FGT Transceivers
2.7. Fractured MAC Avalon ST Client Interface for FHT Transceivers
2.8. Fractured MII PCS-Only Interface for FGT Transceivers
2.9. Fractured MII PCS-Only Interface for FHT Transceivers
2.10. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers
2.11. Fractured PCS66 Interface for OTN/FlexE for FHT Transceivers
2.12. MAC Flow Control Interface
2.13. Status Interface
2.14. Avalon® Memory-Mapped Reconfiguration Interfaces
2.15. Auto-Negotiation and Link Training Interface
2.16. Precision Time Protocol Interface
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1.6. Related Documentation
Links | Description |
---|---|
F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide | This document describes the features, functionality, and implementation of the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Core. |
F-Tile Dynamic Reconfiguration Design Example User Guide | This document describes the F-Tile Dynamic Reconfiguration design example generation, simulation, compilation, and hardware testing. |
F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Release Notes | This document lists the changes and its impact for each version of the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Core. |