F-Tile Ethernet Multirate Intel® FPGA IP User Guide

ID 714307
Date 5/01/2024
Public
Document Table of Contents

2.16.5. RX Timestamp Interface

A separate RX timestamp interface is available for each supported port within a reconfiguration group.

For 400GE rate, width of TX 2-step timestamp is 2x of other Ethernet rates. The interface signals of port 2 and port 0 are concatenated for 400GE port 0 usage as below:
{msb, lsb} == {o_p2_ptp_<signals>, o_p0_ptp_<signals>}
The below table shows the interface details for different number of ports.
Table 71.  Signals of the RX Timestamp InterfaceFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Maximum Number of Ports Applicable Reconfiguration Groups Signal Name
1

FGT:

25GE-1 Reconfigurable

50GE-1 Reconfigurable

FHT:

50GE-1 Reconfigurable

100GE-1 Reconfigurable

Port 0:

o_p0_ptp_rx_its[95:0]

2

FGT:

100GE-2 Reconfigurable

FHT:

100GE-2 Reconfigurable

200GE-2 Reconfigurable

Port 0:

o_p0_ptp_rx_its[95:0]

Port 1:

o_p1_ptp_rx_its[95:0]

4

FGT:

100GE-4 Reconfigurable

400GE-8 Reconfigurable

200GE-4 Reconfigurable

FHT:

100GE-4 Reconfigurable

400GE-4 Reconfigurable

200GE-4 Reconfigurable

Port 0:

o_p0_ptp_rx_its[95:0]

Port 1:

o_p1_ptp_rx_its[95:0]

Port 2:

o_p2_ptp_rx_its[95:0]

Port 3:

o_p3_ptp_rx_its[95:0]