F-Tile Ethernet Multirate Intel® FPGA IP User Guide

Download PDF
ID 714307
Date 5/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile Ethernet Multirate Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide
1. Introduction x
1.1. Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation 1.7. F-Tile Ethernet Multirate IP Core Features and Constraints 1.8. F-Tile Ethernet Multirate IP Core Concepts
1.8. F-Tile Ethernet Multirate IP Core Concepts x
1.8.1. Reconfiguration Group 1.8.2. Base Profile 1.8.3. Secondary Profile 1.8.4. Secondary Profile Group 1.8.5. Startup Profile 1.8.6. Supported Reconfiguration Groups 1.8.7. PTP Timestamp Accuracy Support 1.8.8. Transceiver Lane Mapping
2. Interface Overview x
2.1. Port Numbering Scheme 2.2. Clock Signals 2.3. Reset Signals 2.4. Fractured MAC Segmented Interface for FGT Transceivers 2.5. Fractured MAC Segmented Interface for FHT Transceivers 2.6. Fractured MAC Avalon ST Client Interface for FGT Transceivers 2.7. Fractured MAC Avalon ST Client Interface for FHT Transceivers 2.8. Fractured MII PCS-Only Interface for FGT Transceivers 2.9. Fractured MII PCS-Only Interface for FHT Transceivers 2.10. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers 2.11. Fractured PCS66 Interface for OTN/FlexE for FHT Transceivers 2.12. MAC Flow Control Interface 2.13. Status Interface 2.14. Avalon® Memory-Mapped Reconfiguration Interfaces 2.15. Auto-Negotiation and Link Training Interface 2.16. Precision Time Protocol Interface
2.16. Precision Time Protocol Interface x
2.16.1. PTP Clock Interface 2.16.2. Time-of-Day Interface 2.16.3. TX 2-Step Timestamp Interface 2.16.4. TX 1-Step Timestamp Interface 2.16.5. RX Timestamp Interface 2.16.6. PTP Status Interface 2.16.7. PTP Tile Interface
4. Designing with the IP Core x
4.1. Specifying the IP Core Parameters and Options 4.2. Generated File Structure
4.1. Specifying the IP Core Parameters and Options x
4.1.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Precision Time Protocol
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Ethernet Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide

2.8. Fractured MII PCS-Only Interface for FGT Transceivers

This section describes the fractured interface signals when you select the MII PCS-only client interface in the IP parameter editor.

The datapath interface consists of a fractured interface where the same set of signals is re-used for a single or multiple port datapath connections.

The following tables displays the ports details and the supported variants for each of the reconfiguration groups. The mode selection refers to the Ethernet mode parameter in the F-Tile Ethernet Multirate IP core Profile # IP Configuration tab.

Table 37.  Signals of the Fractured MII PCS-only Interface for 25GE-1 Reconfigurable GroupFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Top Level Interface Mode TX Interface RX Interface

i_tx_mii_d[63:0]

i_tx_mii_valid

i_tx_mii_am

i_tx_mii_c[7:0]

o_tx_mii_ready

o_rx_mii_d[63:0]

o_rx_mii_valid

o_rx_mii_am_valid

o_rx_mii_c[7:0]

1x 25GE-1/

1x 10GE-1

Port 0:

i_tx_mii_d[63:0]

i_tx_mii_valid

i_tx_mii_am

i_tx_mii_c[7:0]

o_tx_mii_ready

Port 0:

o_rx_mii_d[63:0]

o_rx_mii_valid

o_rx_mii_am_valid

o_rx_mii_c[7:0]

Table 38.  Signals of the Fractured MII PCS-only Interface for 50GE-1 Reconfigurable GroupFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Top Level Interface Mode TX Interface RX Interface

i_tx_mii_d[127:0]

i_tx_mii_valid

i_tx_mii_am

i_tx_mii_c[15:0]

o_tx_mii_ready

o_rx_mii_d[127:0]

o_rx_mii_valid

o_rx_mii_am_valid

o_rx_mii_c[15:0]

1x 25GE-1/

1x 10GE-1

Port 0:

i_tx_mii_d[63:0]

i_tx_mii_valid

i_tx_mii_am

i_tx_mii_c[7:0]

o_tx_mii_ready

Port 0:

o_rx_mii_d[63:0]

o_rx_mii_valid

o_rx_mii_am_valid

o_rx_mii_c[7:0]

1x 50GE-1

Port 0:

i_tx_mii_d[127:0]

i_tx_mii_valid

i_tx_mii_am

i_tx_mii_c[15:0]

o_tx_mii_ready

Port 0:

o_rx_mii_d[127:0]

o_rx_mii_valid

o_rx_mii_am_valid

o_rx_mii_c[15:0]

Table 39.  Signals of the Fractured MII PCS-only Interface for 100GE-4 Reconfigurable GroupFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Top Level Interface Mode TX Interface RX Interface

i_tx_mii_d[255:0]

i_tx_mii_valid[3:0]

i_tx_mii_am[3:0]

i_tx_mii_c[31:0]

o_tx_mii_ready[3:0]

o_rx_mii_d[255:0]

o_rx_mii_valid[3:0]

o_rx_mii_am_valid[3:0]

o_rx_mii_c[31:0]

4x 25GE-1/

4x 10GE-1

Port 0:

i_tx_mii_d[63:0]

i_tx_mii_valid[0]

i_tx_mii_am[0]

i_tx_mii_c[7:0]

o_tx_mii_ready[0]

Port 1:

i_tx_mii_d[127:64]

i_tx_mii_valid[1]

i_tx_mii_am[1]

i_tx_mii_c[15:8]

o_tx_mii_ready[1]

Port 2:

id

i_tx_mii_d[191:128]

i_tx_mii_valid[2]

i_tx_mii_am[2]

i_tx_mii_c[23:16]

o_tx_mii_ready[2]

Port 3:

i_tx_mii_d[255:192]

i_tx_mii_valid[3]

i_tx_mii_am[3]

i_tx_mii_c[31:24]

o_tx_mii_ready[3]

Port 0:

o_rx_mii_d[63:0]

o_rx_mii_valid[0]

o_rx_mii_am_valid[0]

o_rx_mii_c[7:0]

Port 1:

o_rx_mii_d[127:64]

o_rx_mii_valid[1]

o_rx_mii_am_valid[1]

o_rx_mii_c[15:8]

Port 2:

o_rx_mii_d[191:128]

o_rx_mii_valid[2]

o_rx_mii_am_valid[2]

o_rx_mii_c[23:16]

Port 3:

o_rx_mii_d[255:192]

o_rx_mii_valid[3]

o_rx_mii_am_valid[3]

o_rx_mii_c[31:24]

2x 50GE-2/

2x 50GE-1

Port 0:

i_tx_mii_d[127:0]

i_tx_mii_valid[0]

i_tx_mii_am[0]

i_tx_mii_c[15:0]

o_tx_mii_ready[0]

Port 2:

i_tx_mii_d[255:128]

i_tx_mii_valid[2]

i_tx_mii_am[2]

i_tx_mii_c[31:16]

o_tx_mii_ready[2]

Port 0:

o_rx_mii_d[127:0]

o_rx_mii_valid[0]

o_rx_mii_am_valid[0]

o_rx_mii_c[15:0]

Port 2:

o_rx_mii_d[255:128]

o_rx_mii_valid[2]

o_rx_mii_am_valid[2]

o_rx_mii_c[31:16]

1x 100GE-4/

1x 100GE-2

Port 0:

i_tx_mii_d[255:0]

i_tx_mii_valid[0]

i_tx_mii_am[0]

i_tx_mii_c[31:0]

o_tx_mii_ready[0]

Port 0:

o_rx_mii_d[255:0]

o_rx_mii_valid[0]

o_rx_mii_am_valid[0]

o_rx_mii_c[31:0]

Table 40.  Signals of the Fractured MII PCS-only Interface for 100GE-2 Reconfigurable GroupFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Top Level Interface Mode TX Interface RX Interface

i_tx_mii_d[255:0]

i_tx_mii_valid[1:0]

i_tx_mii_am[1:0]

i_tx_mii_c[31:0]

o_tx_mii_ready[1:0]

o_rx_mii_d[255:0]

o_rx_mii_valid[1:0]

o_rx_mii_am_valid[1:0]

o_rx_mii_c[31:0]

1x 100GE-2

Port 0:

i_tx_mii_d[255:0]

i_tx_mii_valid[0]

i_tx_mii_am[0]

i_tx_mii_c[31:0]

o_tx_mii_ready[0]

Port 0:

o_rx_mii_d[255:0]

o_rx_mii_valid[0]

o_rx_mii_am_valid[0]

o_rx_mii_c[31:0]

2x 50GE-1

Port 0:

i_tx_mii_d[127:0]

i_tx_mii_valid[0]

i_tx_mii_am[0]

i_tx_mii_c[15:0]

o_tx_mii_ready[0]

Port 1:

i_tx_mii_d[255:128]

i_tx_mii_valid[1]

i_tx_mii_am[1]

i_tx_mii_c[31:16]

o_tx_mii_ready[1]

Port 0:

o_rx_mii_d[127:0]

o_rx_mii_valid[0]

o_rx_mii_am_valid[0]

o_rx_mii_c[15:0]

Port 1:

o_rx_mii_d[255:128]

o_rx_mii_valid[1]

o_rx_mii_am_valid[1]

o_rx_mii_c[31:16]

2x 25GE-1/

2x 10GE-1

Port 0:

i_tx_mii_d[63:0]

i_tx_mii_valid[0]

i_tx_mii_am[0]

i_tx_mii_c[7:0]

o_tx_mii_ready[0]

Port 1:

i_tx_mii_d[191:128]

i_tx_mii_valid[1]

i_tx_mii_am[1]

i_tx_mii_c[23:16]

o_tx_mii_ready[1]

Port 0:

o_rx_mii_d[63:0]

o_rx_mii_valid[0]

o_rx_mii_am_valid[0]

o_rx_mii_c[7:0]

Port 1:

o_rx_mii_d[191:128]

o_rx_mii_valid[1]

o_rx_mii_am_valid[1]

o_rx_mii_c[23:16]

1x 50GE-2

Port 0:

i_tx_mii_d[127:0]

i_tx_mii_valid[0]

i_tx_mii_am[0]

i_tx_mii_c[15:0]

o_tx_mii_ready[0]

Port 0:

o_rx_mii_d[127:0]

o_rx_mii_valid[0]

o_rx_mii_am_valid[0]

o_rx_mii_c[15:0]

Table 41.  Signals of the Fractured MII PCS-only Interface for 400GE-8 Reconfigurable GroupFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Top Level Interface Mode TX Interface RX Interface

i_tx_mii_d[1023:0]

i_tx_mii_valid[3:0]

i_tx_mii_am[3:0]

i_tx_mii_c[127:0]

o_tx_mii_ready[3:0]

o_rx_mii_d[1023:0]

o_rx_mii_valid[3:0]

o_rx_mii_am_valid[3:0]

o_rx_mii_c[127:0]

1x 400GE-8

Port 0:

i_tx_mii_d[1023:0]

i_tx_mii_valid[0]

i_tx_mii_am[0]

i_tx_mii_c[127:0]

o_tx_mii_ready[0]

Port 0:

o_rx_mii_d[1023:0]

o_rx_mii_valid[0]

o_rx_mii_am_valid[0]

o_rx_mii_c[127:0]

2x 200GE-4

Port 0:

i_tx_mii_d[511:0]

i_tx_mii_valid[0]

i_tx_mii_am[0]

i_tx_mii_c[63:0]

o_tx_mii_ready[0]

Port 2:

i_tx_mii_d[1023:512]

i_tx_mii_valid[2]

i_tx_mii_am[2]

i_tx_mii_c[127:64]

o_tx_mii_ready[2]

Port 0:

o_rx_mii_d[511:0]

o_rx_mii_valid[0]

o_rx_mii_am_valid[0]

o_rx_mii_c[63:0]

Port 2:

o_rx_mii_d[1023:512]

o_rx_mii_valid[2]

o_rx_mii_am_valid[2]

o_rx_mii_c[127:64]

4x 100GE-2

Port 0:

i_tx_mii_d[255:0]

i_tx_mii_valid[0]

i_tx_mii_am[0]

i_tx_mii_c[31:0]

o_tx_mii_ready[0]

Port 1:

i_tx_mii_d[511:256]

i_tx_mii_valid[1]

i_tx_mii_am[1]

i_tx_mii_c[63:32]

o_tx_mii_ready[1]

Port 2:

i_tx_mii_d[767:512]

i_tx_mii_valid[2]

i_tx_mii_am[2]

i_tx_mii_c[95:64]

o_tx_mii_ready[2]

Port 3:

i_tx_mii_d[1023:768]

i_tx_mii_valid[3]

i_tx_mii_am[3]

i_tx_mii_c[127:96]

o_tx_mii_ready[3]

Port 0:

o_rx_mii_d[255:0]

o_rx_mii_valid[0]

o_rx_mii_am_valid[0]

o_rx_mii_c[31:0]

Port 1:

o_rx_mii_d[511:256]

o_rx_mii_valid[1]

o_rx_mii_am_valid[1]

o_rx_mii_c[63:32]

Port 2:

o_rx_mii_d[767:512]

o_rx_mii_valid[2]

o_rx_mii_am_valid[2]

o_rx_mii_c[95:64]

Port 3:

o_rx_mii_d[1023:768]

o_rx_mii_valid[3]

o_rx_mii_am_valid[3]

o_rx_mii_c[127:96]

Table 42.  Signals of the Fractured MII PCS-only Interface for 200GE-4 Reconfigurable GroupFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Top Level Interface Mode TX Interface RX Interface

i_tx_mii_d[511:0]

i_tx_mii_valid[3:0]

i_tx_mii_am[3:0]

i_tx_mii_c[63:0]

o_tx_mii_ready[3:0]

o_rx_mii_d[511:0]

o_rx_mii_valid[3:0]

o_rx_mii_am_valid[3:0]

o_rx_mii_c[63:0]

1x 200GE-4

Port 0:

i_tx_mii_d[511:0]

i_tx_mii_valid[3:0]

i_tx_mii_am[3:0]

i_tx_mii_c[63:0]

o_tx_mii_ready[3:0]

Port 0:

o_rx_mii_d[511:0]

o_rx_mii_valid[3:0]

o_rx_mii_am_valid[3:0]

o_rx_mii_c[63:0]

2x 100GE-2

Port 0:

i_tx_mii_d[255:0]

i_tx_mii_valid[0]

i_tx_mii_am[0]

i_tx_mii_c[31:0]

o_tx_mii_ready[0]

Port 2:

i_tx_mii_d[511:256]

i_tx_mii_valid[2]

i_tx_mii_am[2]

i_tx_mii_c[63:32]

o_tx_mii_ready[2]

Port 0:

o_rx_mii_d[255:0]

o_rx_mii_valid[0]

o_rx_mii_am_valid[0]

o_rx_mii_c[31:0]

Port 2:

o_rx_mii_d[511:256]

o_rx_mii_valid[2]

o_rx_mii_am_valid[2]

o_rx_mii_c[63:32]

4x 50GE-1

Port 0:

i_tx_mii_d[127:0]

i_tx_mii_valid[0]

i_tx_mii_am[0]

i_tx_mii_c[15:0]

o_tx_mii_ready[0]

Port 1:

i_tx_mii_d[255:128]

i_tx_mii_valid[1]

i_tx_mii_am[1]

i_tx_mii_c[31:16]

o_tx_mii_ready[1]

Port 2:

i_tx_mii_d[383:256]

i_tx_mii_valid[2]

i_tx_mii_am[2]

i_tx_mii_c[47:32]

o_tx_mii_ready[2]

Port 3:

i_tx_mii_d[511:384]

i_tx_mii_valid[3]

i_tx_mii_am[3]

i_tx_mii_c[63:48]

o_tx_mii_ready[3]

Port 0:

o_rx_mii_d[127:0]

o_rx_mii_valid[0]

o_rx_mii_am_valid[0]

o_rx_mii_c[15:0]

Port 1:

o_rx_mii_d[255:128]

o_rx_mii_valid[1]

o_rx_mii_am_valid[1]

o_rx_mii_c[31:16]

Port 2:

o_rx_mii_d[383:256]

o_rx_mii_valid[2]

o_rx_mii_am_valid[2]

o_rx_mii_c[47:32]

Port 3:

o_rx_mii_d[511:384]

o_rx_mii_valid[3]

o_rx_mii_am_valid[3]

o_rx_mii_c[63:48]

2x 50GE-2

Port 0:

i_tx_mii_d[127:0]

i_tx_mii_valid[0]

i_tx_mii_am[0]

i_tx_mii_c[15:0]

o_tx_mii_ready[0]

Port 2:

i_tx_mii_d[383:256]

i_tx_mii_valid[2]

i_tx_mii_am[2]

i_tx_mii_c[47:32]

o_tx_mii_ready[2]

Port 0:

o_rx_mii_d[127:0]

o_rx_mii_valid[0]

o_rx_mii_am_valid[0]

o_rx_mii_c[15:0]

Port 2:

o_rx_mii_d[383:256]

o_rx_mii_valid[2]

o_rx_mii_am_valid[2]

o_rx_mii_c[47:32]

1x 100GE-4

Port 0:

i_tx_mii_d[255:0]

i_tx_mii_valid[0]

i_tx_mii_am[0]

i_tx_mii_c[31:0]

o_tx_mii_ready[0]

Port 0:

o_rx_mii_d[255:0]

o_rx_mii_valid[0]

o_rx_mii_am_valid[0]

o_rx_mii_c[31:0]

Level Two Title