F-Tile Ethernet Multirate Intel® FPGA IP User Guide

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ID 714307
Date 5/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile Ethernet Multirate Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide
1. Introduction x
1.1. Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation 1.7. F-Tile Ethernet Multirate IP Core Features and Constraints 1.8. F-Tile Ethernet Multirate IP Core Concepts
1.8. F-Tile Ethernet Multirate IP Core Concepts x
1.8.1. Reconfiguration Group 1.8.2. Base Profile 1.8.3. Secondary Profile 1.8.4. Secondary Profile Group 1.8.5. Startup Profile 1.8.6. Supported Reconfiguration Groups 1.8.7. PTP Timestamp Accuracy Support 1.8.8. Transceiver Lane Mapping
2. Interface Overview x
2.1. Port Numbering Scheme 2.2. Clock Signals 2.3. Reset Signals 2.4. Fractured MAC Segmented Interface for FGT Transceivers 2.5. Fractured MAC Segmented Interface for FHT Transceivers 2.6. Fractured MAC Avalon ST Client Interface for FGT Transceivers 2.7. Fractured MAC Avalon ST Client Interface for FHT Transceivers 2.8. Fractured MII PCS-Only Interface for FGT Transceivers 2.9. Fractured MII PCS-Only Interface for FHT Transceivers 2.10. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers 2.11. Fractured PCS66 Interface for OTN/FlexE for FHT Transceivers 2.12. MAC Flow Control Interface 2.13. Status Interface 2.14. Avalon® Memory-Mapped Reconfiguration Interfaces 2.15. Auto-Negotiation and Link Training Interface 2.16. Precision Time Protocol Interface
2.16. Precision Time Protocol Interface x
2.16.1. PTP Clock Interface 2.16.2. Time-of-Day Interface 2.16.3. TX 2-Step Timestamp Interface 2.16.4. TX 1-Step Timestamp Interface 2.16.5. RX Timestamp Interface 2.16.6. PTP Status Interface 2.16.7. PTP Tile Interface
4. Designing with the IP Core x
4.1. Specifying the IP Core Parameters and Options 4.2. Generated File Structure
4.1. Specifying the IP Core Parameters and Options x
4.1.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Precision Time Protocol
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Ethernet Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide

2.3. Reset Signals

Each of the Ethernet Multirate IP core ports has its own set of reset signals. The i_reconfig_reset reset signal is shared. The rx_pcs_ready and tx_lanes_stable signals are available on per port basis.
Table 15.  Reset SignalsAll specified resets are asynchronous.
Port Name Number of Ports I/O Direction Description
i_reconfig_reset 1, 2, or 4 Input Reconfiguration reset. Resets the Avalon® memory-mapped interface connections to the F-tile and resets Soft CSR. It does not reset F-tile CSRs. Active high. Must be asserted once upon power-up.
i_p0_rst_n 1, 2, or 4 Input

Active-low reset asynchronous signal.

This reset leads to assertion of the o_p0_rst_ack_n output signal.

Do not deassert until the o_p0_rst_ack_n output signal deasserts.

  • Resets the TX interface, including the TX PMA, TX PCS, TX MAC, and TX AIB.
  • Resets the RX interface, including the RX PMA, RX PCS, RX MAC, and RX AIB.
o_p0_rst_ack_n 1, 2, or 4 Output

Acknowledgement signal for the i_p0_rst_n reset. Active low.

i_p0_tx_rst_n 1, 2, or 4 Input Resets the selected port 0 TX datapath. Active low.
o_p0_tx_rst_ack_n 1, 2, or 4 Output Port 0 TX datapath reset acknowledgement. Active low.
i_p0_rx_rst_n 1, 2, or 4 Input Resets the selected port 0 RX datapath. Active low.
o_p0_rx_rst_ack_n 1, 2, or 4 Output Port 0 RX datapath reset acknowledgement. Active low.
o_p0_tx_lanes_stable 1, 2, or 4 Output Port 0 TX datapath is out of reset and ready.
o_p0_rx_pcs_ready 1, 2, or 4 Output Port 0 RX datapath is out of reset and ready.
i_p1_rst_n 2 or 4 Input

Active-low reset asynchronous signal.

This reset leads to assertion of the o_p1_rst_ack_n output signal.

Do not deassert until the o_p1_rst_ack_n output signal deasserts.

  • Resets the TX interface, including the TX PMA, TX PCS, TX MAC, and TX AIB.
  • Resets the RX interface, including the RX PMA, RX PCS, RX MAC, and RX AIB.
o_p1_rst_ack_n 2 or 4 Output

Acknowledgement signal for the i_p1_rst_n reset. Active low.

i_p1_tx_rst_n 2 or 4 Input Resets the selected port 1 TX datapath. Active low.
o_p1_tx_rst_ack_n 2 or 4 Output Port 1 TX datapath reset acknowledgement. Active low.
i_p1_rx_rst_n 2 or 4 Input Resets the selected port 1 RX datapath. Active low.
o_p1_rx_rst_ack_n 2 or 4 Output Port 1 RX datapath reset acknowledgement. Active low.
o_p1_tx_lanes_stable 2 or 4 Output Port 1 TX datapath is out of reset and ready.
o_p1_rx_pcs_ready 2 or 4 Output Port 1 RX datapath is out of reset and ready.
i_p2_rst_n 4 Input

Active-low reset asynchronous signal.

Active-low reset asynchronous signal. This reset leads to assertion of the o_p2_rst_ack_n output signal.

Do not deassert until the o_p2_rst_ack_n output signal deasserts.

  • Resets the TX interface, including the TX PMA, TX PCS, TX MAC, and TX AIB.
  • Resets the RX interface, including the RX PMA, RX PCS, RX MAC, and RX AIB.
o_p2_rst_ack_n 4 Output

Acknowledgement signal for the i_p2_rst_n reset. Active low.

i_p2_tx_rst_n 4 Input Resets the selected port 2 TX datapath. Active low.
o_p2_tx_rst_ack_n 4 Output Port 2 TX datapath reset acknowledgement. Active low.
i_p2_rx_rst_n 4 Input Resets the selected port 2 RX datapath. Active low.
o_p2_rx_rst_ack_n 4 Output Port 2 RX datapath reset acknowledgement. Active low.
o_p2_tx_lanes_stable 4 Output Port 2 TX datapath is out of reset and ready.
o_p2_rx_pcs_ready 4 Output Port 2 RX datapath is out of reset and ready.
i_p3_rst_n 4 Input

Active-low reset asynchronous signal.

This reset leads to assertion of the o_p3_rst_ack_n output signal.

Do not deassert until the o_p3_rst_ack_n output signal deasserts.

  • Resets the TX interface, including the TX PMA, TX PCS, TX MAC, and TX AIB.
  • Resets the RX interface, including the RX PMA, RX PCS, RX MAC, and RX AIB.
o_p3_rst_ack_n 4 Output

Acknowledgement signal for the i_p3_rst_n reset. Active low.

i_p3_tx_rst_n 4 Input Resets the selected port 3 TX datapath. Active low.
o_p3_tx_rst_ack_n 4 Output Port 3 TX datapath reset acknowledgement. Active low.
i_p3_rx_rst_n 4 Input Resets the selected port 3 RX datapath. Active low.
o_p3_rx_rst_ack_n 4 Output Port 3 RX datapath reset acknowledgement. Active low.
o_p3_tx_lanes_stable 4 Output Port 3 TX datapath is out of reset and ready.
o_p3_rx_pcs_ready 4 Output Port 3 RX datapath is out of reset and ready.
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