F-Tile Ethernet Multirate Intel® FPGA IP User Guide

ID 714307
Date 5/01/2024
Public
Document Table of Contents

2.12. MAC Flow Control Interface

The MAC flow control interface is available for each supported port within a reconfiguration group.
The table displays the interface signals for different numbers of ports. All interface signals are clocked by the i_clk_tx clock. For 10GE/25GE channels, all interface signals are asynchronous.
Table 63.  Signals of the MAC Flow Control Interface SignalsFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Number of Ports Signal Name
1

Port 0:

i_p0_tx_pause

i_p0_tx_pfc[7:0]

o_p0_rx_pause

o_p0_rx_pfc[7:0]

2

Port 0:

i_p0_tx_pause

i_p0_tx_pfc[7:0]

o_p0_rx_pause

o_p0_rx_pfc[7:0]

Port 1:

i_p1_tx_pause

i_p1_tx_pfc[7:0]

o_p1_rx_pause

o_p1_rx_pfc[7:0]

4

Port 0:

i_p0_tx_pause

i_p0_tx_pfc[7:0]

o_p0_rx_pause

o_p0_rx_pfc[7:0]

Port 1:

i_p1_tx_pause

i_p1_tx_pfc[7:0]

o_p1_rx_pause

o_p1_rx_pfc[7:0]

Port 2:

i_p2_tx_pause

i_p2_tx_pfc[7:0]

o_p2_rx_pause

o_p2_rx_pfc[7:0]

Port 3:

i_p3_tx_pause

i_p3_tx_pfc[7:0]

o_p3_rx_pause

o_p3_rx_pfc[7:0]