Visible to Intel only — GUID: hdz1603918756868
Ixiasoft
Visible to Intel only — GUID: hdz1603918756868
Ixiasoft
2.4.1.2. FGT and System PLL Reference Clock Network
There are ten reference clocks for FGT PMAs. Eight of the FGT reference clocks (refclk[0]-refclk[7]) can be configured as input ports. The remaining two FGT reference clocks are bidirectional. The FGT reference clock frequency range is 25-380 MHz (25-100 MHz for HDMI only).
refclk[0]-refclk[7] can also be shared as reference clocks for system PLLs. Refer to System PLL for details. The system PLL reference clock frequency range is 100-380 MHz.
There are three FGT and system PLL reference clock types.
- Global reference clocks are accessible by four FGT quads.
- Regional reference clocks are accessible by two quads.
- Local reference clocks are accessible by one quad.
Global and regional reference clocks are also accessible by system PLLs. See the following table for details.
Any hard IP that spans FGT quads must use a reference clock that is accessible by all quads. For example, PCIe* x16 can only use refclk[2], refclk[3], refclk[4], and refclk[5].
FGT and System PLL Reference Clocks | Type | Direction | Accessible to FGT PMAs? | Accessible FGT Quads | Accessible to System PLLs? | Accessible System PLL |
---|---|---|---|---|---|---|
refclk[0] | Regional | Input | Yes | Quad0, Quad1 | Yes | System PLL 1, 2, and 3 |
refclk[1] | Regional | Input | Yes | Quad0, Quad1 | Yes | System PLL 1, 2, and 3 |
refclk[2] | Global | Input | Yes | Quad0, Quad1, Quad2, Quad3 | Yes | System PLL 1, 2, and 3 |
refclk[3] | Global | Input | Yes | Quad0, Quad1, Quad2, Quad3 | Yes | System PLL 1, 2, and 3 |
refclk[4] | Global | Input | Yes | Quad0, Quad1, Quad2, Quad3 | Yes | System PLL 1, 2, and 3 |
refclk[5] | Global | Input | Yes | Quad0, Quad1, Quad2, Quad3 | Yes | System PLL 1, 2, and 3 |
refclk[6] | Regional | Input | Yes | Quad2, Quad3 | Yes | System PLL 1, 2, and 3 |
refclk[7] | Regional | Input | Yes | Quad2, Quad3 | Yes | System PLL 1, 2, and 3 |
refclk[8] | Local | Input or output 11 | Yes | Quad2 | No | N/A |
refclk[9] | Local | Input or output11 | Yes | Quad3 | No | N/A |
- This RX recovered clock is valid after the respective PMA achieves lock-to-data (LTD).
- The primary use case of this configuration is the CPRI protocol. Refer to the F-Tile CPRI PHY Intel® FPGA IP User Guide for the supported recovered clock frequencies.