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3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
The tx_parallel_data bit and rx_parallel_data bit width depends on the PMA width and Number of PMA lanes IP parameters. Use the following equation to determine the total tx_parallel_data or rx_parallel_data bit width:
27Total tx_parallel_data or rx_parallel_data Bit Width Equation:
tx/rx_parallel_data[(80*N*X)-1:0]
Where:
- N = Number of PMA lanes value from 1 to 16.
- X = Number of streams for the PMA configuration. Depending on PMA width, X can be 1, 2, or 4.
Refer to Variables Defining Bits for the Interfacing Ports in Port and Signal Reference for full variable definitions.
The tx/rx_parallel_data signals include the valid parallel data bits and other functionality bits, such as the data valid bit, the write enable for TX core interface FIFO in elastic mode bit, the RX deskew bit, and the alignment market bits (for FEC mode). These signals travel to and from the FPGA fabric to the F-tile, and are clocked by the same parallel clock. This parallel clock can be a PMA clock or System PLL clock.
Example 1: Total tx/rx_parallel_data Bit Width with 2 PMA Lanes (N=2) and 8-bit PMA Width (X=1)
tx_parallel_data [(80*2*1)-1:0] = tx_parallel_data [159:0]
rx_parallel_data [(80*2*1)-1:0] = rx_parallel_data [159:0]
Example 2: Total tx/rx_parallel_data Bit Width with 4 PMA Lanes (N=4) and 64-bit PMA Width (X=2)
tx_parallel_data [(80*4*2)-1:0] = tx_parallel_data [639:0]
rx_parallel_data [(80*4*8)-1:0] = rx_parallel_data [639:0]
Parallel Data Mapping information for TX and RX
If the PMA width is less than or equal to 32, D=PMA width.
If the PMA width is 64 or 128, D=32.
The lower case x is defined as x=0 to X-1. For a given lane, n and given stream x, you can calculate the TX and RX parallel data information according to the following tables:
TX Parallel Data | MSB | LSB |
---|---|---|
Write Enable for TX Core FIFO in Elastic Mode 28 | 79 + (80 * x) +(80 *n * X) | |
TX Data (Upper Data bits) | (40 + D-1) + (80 * x) + (80 *n * X) | 40 + (80 * x) + (80 *n * X) |
TX PMA Interface Data Valid Bit 29 30 | 38 + (80 * x) + (80 *n * X) | |
TX Data (Lower Data bits) | D-1 + (80 * x) + (80 *n * X) | 0 + (80 * x) +(80 *n * X) |
RX Parallel Data | MSB | LSB |
---|---|---|
Data valid for RX Core FIFO in Elastic Mode (25) | 79 + (80 * x) + (80 *n * X) | |
RX Deskew 31 | 78 + (80 * x) + (80 *n * X) | |
RX Data (Upper Data bits) | (40 + D-1) + (80 * x) + (80 *n * X ) | 40 + (80 * x) + (80 *n * X) |
RX PMA Interface Data Valid Bit (26) | 38 + (80 * x) + (80 *n * X) | |
RX Data (Lower Data bits) | D-1 + (80 * x) + (80 *n * X) | 0 + (80 * x) + (80 *n * X) |
TX Parallel Data | MSB | LSB |
---|---|---|
Write Enable for TX Core FIFO in Elastic Mode (25) | 79 + (80 *n) | |
TX PMA Interface Data Valid Bit (26) (27) | 38 + (80 *n) | |
TX Data | D-1 + (80 *n) | 0 + (80 *n) |
RX Parallel Data | MSB | LSB |
---|---|---|
Data valid for RX Core FIFO in Elastic Mode (25) | 79 + (80 *n) | |
RX PMA Interface Data Valid Bit (26) | 38 + (80 *n) | |
RX Data | D-1 + (80 *n) | 0 + (80 *n) |
TX Parallel Data | MSB | LSB |
---|---|---|
Alignment Marker32 | 77 + (80 * x) +(80 *n * X) | |
TX Data (Upper 33 bits) | 72 + (80 * x) + (80 *n * X) | 40 + (80 * x) + (80 *n * X) |
TX PMA Interface Data Valid Bit (26) (27) | 38 + (80 * x) + (80 *n * X) | |
Alignment Marker (25) | 37 + (80 * x) + (80 *n * X) | |
TX Data (Lower 31 bits) | 32 + (80 * x) + (80 *n * X) | 2 + (80 * x) + (80 *n * X) |
Sync Head | 1 + (80 * x) + (80 *n * X) | 0 + (80 * x) + (80 *n * X) |
RX Parallel Data | MSB | LSB |
---|---|---|
RX Deskew 33 | 78 + (80 * x) + (80 *n * X) | |
RX Data (Upper 33 bits) | 72 + (80 * x) + (80 *n * X) | 40 + (80 * x) + (80 *n * X) |
RX PMA Interface Data Valid Bit (26) 34 | 38 | |
Alignment Marker (29) | 37 | |
RX Data (Lower 31 bits) | 32 + (80 * x) + (80 *n * X) | 2 + (80 * x) + (80 *n * X) |
Sync Head | 1 + (80 * x) + (80 *n * X) | 0 + (80 * x) + (80 *n * X) |
- Parallel Data Mapping Information
- TX and RX Parallel Data Mapping Information for Different Configurations
- Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1)
- Example of TX Parallel Data for PMA width = 64 (X=2)
- Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode