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3.11.6. Logical Avalon® Memory-Mapped Port Indexing
This section explains how to access the FGT PMA lanes if your design has more than four FGT PMA lanes that span across multiple FGT quads, or if you place the FGT PMA lane across different FGT quads. You need to know how to control the logical Avalon® memory-mapped port indexing if you are using the shared reconfiguration interface. (Enable separate Avalon interface per PMA = Off). The Logical Avalon® Memory-Mapped Port Indexing is only applicable for FGT PMA lanes and not for FHT PMA lanes.
If your design has the Enable separate Avalon interface per fracture = On feature enabled, each datapath and PMA Avalon® memory-mapped interface has its own reconfiguration interface and you can directly access the port’s register address without following the logical port indexing instruction explained in this section.
- 14 bits for the datapath Avalon memory-mapped reconfiguration interface (reconfig_pdp_address[13:0])
- 18 bits for the PMA Avalon memory-mapped reconfiguration interface (reconfig_xcvr_address[17:0])
The reconfiguration address space grows as a function of the following equation:
log2(N)(where N = number of lanes), for an increase in the number of PMA lanes. The additional MSB bits of the reconfiguration address bus represent the logical Avalon® memory-mapped port index value. Refer to MSB Address Bits for PMA Logical Avalon® Memory-Mapped Reconfiguration Port Index Value and MSB Address Bits for Datapath Logical Avalon® Memory-Mapped Reconfiguration Port Index Value for more information.
For example, if you enable 16 PMA lanes in your design, for the PMA Avalon® memory-mapped interface, the total reconfiguration address bus is reconfig_xcvr_address[21:0]. The PMA Avalon® memory-mapped interfaces MSB address bits (reconfig_xcvr_address[21:18]) provide the logical mapping to access different lanes and quads based on the number of PMA lanes. The 4 additional MSB address bits (reconfig_xcvr_address[21:18]) are a logical representation of the PMA Avalon® memory-mapped interface port. You can use them to read or write to the individual PMA Avalon® memory-mapped interface defined within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP. The following table shows the MSB address bits for PMA logical Avalon® memory-mapped port indexing with the number of PMA lanes configured in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP.
PMA Lane Set in GUI(s) | Reconfiguration Address Bus | MSB Address Bits for PMA Logical Avalon® Memory-Mapped Port Indexing | PMA Logical Avalon® Memory-Mapped Port Indexing (value=hex) |
---|---|---|---|
1 | reconfig_xcvr_address[17:0] | Not Applicable | 0 |
2 | reconfig_xcvr_address[18:0] | [18] | 0,1 |
4 | reconfig_xcvr_address[19:0] | [19:18] | 0,1,2,3 |
6, 8 | reconfig_xcvr_address[20:0] | [20:18] | 0,1,2,3,4,5,6,7 |
12, 16 | reconfig_xcvr_address[21:0] | [21:18] | 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F |
Similarly, the datapath Avalon® memory-mapped interface's MSB address bits (reconfig_pdp_address[17:14]) provide the logical mapping to access different lanes and quads based on the number of PMA lanes. The datapath Avalon® memory-mapped interfaces MSB address bits (reconfig_pdp_address[17:14]) are a logical representation of the datapath Avalon® memory-mapped interface port. You can use them to read or write to the individual datapath Avalon® memory-mapped interface ports defined within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP. The following table shows the MSB address bits for datapath logical Avalon® memory-mapped port indexing with the number of PMA lanes configured in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP.
PMA Lane Set in GUI(s) | Reconfiguration Address Bus | MSB Address Bits for Datapath Logical Avalon® Memory-Mapped Port Indexing | Datapath Logical Avalon® Memory-Mapped Port Indexing (value= hex) |
---|---|---|---|
1 | reconfig_pdp_address[13:0] | Not Applicable | 0 |
2 | reconfig_pdp_address[14:0] | [14] | 0,1 |
4 | reconfig_pdp_address[15:0] | [15:14] | 0,1,2,3 |
6, 8 | reconfig_pdp_address[16:0] | [16:14] | 0,1,2,3,4,5,6,7 |
12, 16 | reconfig_pdp_address[17:0] | [17:14] | 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F |
- If the Avalon® memory-mapped port index value = 0x0 and the offset address is 0x48000. You write to 0x048000.
- If the Avalon® memory-mapped port index value = 0x2 and the offset address is 0x58000. You write to 0x258000.
Quad | Lane | Datapath and PMA Logical Avalon® Memory-Mapped Port Index [3:0] | Offset Address |
---|---|---|---|
0 | 0 | 0x0 | 0x40000 |
1 | 0x1 | 0x48000 | |
2 | 0x2 | 0x50000 | |
3 | 0x3 | 0x58000 | |
1 | 0 | 0x4 | 0x40000 |
1 | 0x5 | 0x48000 | |
2 | 0x6 | 0x50000 | |
3 | 0x7 | 0x58000 | |
2 | 0 | 0x8 | 0x40000 |
1 | 0x9 | 0x48000 | |
2 | 0xA | 0x50000 | |
3 | 0xB | 0x58000 | |
3 | 0 | 0xC | 0x40000 |
1 | 0xD | 0x48000 | |
2 | 0xE | 0x50000 | |
3 | 0xF | 0x58000 |