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1. F-tile Overview
2. F-tile Architecture
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP
5. Implementing the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP
6. F-tile PMA/FEC Direct PHY Design Implementation
7. Supported Tools
8. Debugging F-Tile Transceiver Links
9. F-tile Architecture and PMA and FEC Direct PHY IP User Guide Archives
10. Document Revision History for F-tile Architecture and PMA and FEC Direct PHY IP User Guide
2.1.1. FHT and FGT PMAs
2.1.2. 400G Hard IP and 200G Hard IP
2.1.3. PMA Data Rates
2.1.4. FEC Architecture
2.1.5. PCIe* Hard IP
2.1.6. Bonding Architecture
2.1.7. Deskew Logic
2.1.8. Embedded Multi-die Interconnect Bridge (EMIB)
2.1.9. IEEE 1588 Precision Time Protocol for Ethernet
2.1.10. Clock Networks
2.1.11. Reconfiguration Interfaces
2.2.1. PMA-to-Fracture Mapping
2.2.2. Determining Which PMA to Map to Which Fracture
2.2.3. Hard IP Placement Rules
2.2.4. IEEE 1588 Precision Time Protocol Placement Rules
2.2.5. Topologies
2.2.6. FEC Placement Rules
2.2.7. Clock Rules and Restrictions
2.2.8. Bonding Placement Rules
2.2.9. Preserving Unused PMA Lanes
2.2.2.1. Implementing One 200GbE-4 Interface with 400G Hard IP and FHT
2.2.2.2. Implementing One 200GbE-2 Interface with 400G Hard IP and FHT
2.2.2.3. Implementing One 100GbE-1 Interface with 400G Hard IP and FHT
2.2.2.4. Implementing One 100GbE-4 Interface with 400G Hard IP and FGT
2.2.2.5. Implementing One 10GbE-1 Interface with 200G Hard IP and FGT
2.2.2.6. Implementing Three 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.7. Implementing One 50GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.8. Implementing One 100GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.9. Implementing Two 100GbE-1 and One 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.10. Implementing 100GbE-1, 100GbE-2, and 50GbE-1 Interfaces with 400G Hard IP and FHT
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview
3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP
3.3. Configuring the IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting Reset
3.9. Bonding Implementation
3.10. Independent Port Configurations
3.11. Configuration Registers
3.12. Configurable Intel® Quartus® Prime Software Settings
3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. RS-FEC Signals
3.4.5. Custom Cadence Control and Status Signals
3.4.6. TX PMA Status Signals
3.4.7. RX PMA Status Signals
3.4.8. TX and RX PMA and Core Interface FIFO Signals
3.4.9. PMA Avalon® Memory Mapped Interface Signals
3.4.10. Datapath Avalon® Memory Mapped Interface Signals
3.5.1. Parallel Data Mapping Information
3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations
3.5.3. Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1)
3.5.4. Example of TX Parallel Data for PMA width = 64 (X=2)
3.5.5. Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Reset Signals—Descriptions
3.8.5. Status Signals—Descriptions
3.8.6. Run-time Reset Sequence—TX
3.8.7. Run-time Reset Sequence—RX
3.8.8. Run-time Reset Sequence—TX + RX
3.8.9. Run-time Reset Sequence—TX with FEC
6.1. Implementing the F-tile PMA/FEC Direct PHY Design
6.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
6.3. Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
6.4. Instantiating the F-Tile Reference and System PLL Clocks Intel® FPGA IP
6.5. Enabling Custom Cadence Generation Ports and Logic
6.6. Connecting the F-tile PMA/FEC Direct PHY Design IP
6.7. Simulating the F-Tile PMA/FEC Direct PHY Design
6.8. F-tile Interface Planning
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5.3. Hardware Flow Using the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP
You can access the FHT and FGT PMA registers using the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP.
Here are the steps you need to follow to add the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP to work with a F-Tile PMA/FEC Direct PHY Intel® FPGA IP design.
- Add the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP into your design and enable the read_data_valid port as shown in the following figures.
Figure 87. F-Tile Global Avalon Memory-Mapped Interface Intel FPGA IPFigure 88. F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP Settings
- Add the JTAG to Avalon® Master Bridge Intel FPGA IP into your design.
Figure 89. JTAG to Avalon® Master Bridge Intel FPGA IP
- Declare wires to connect the g_avmm interface to the jtag_master ports as shown in the following figure.
Note: The g_avmm_address port of g_avmm interface is 18 bits and the master_address port of jtag_master is 32 bits.Note: You need to enable the readdatavalid port in the JTAG to Avalon® Master Bridge Intel FPGA IP and connect it to the corresponding F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP port.Figure 90. F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP to JTAG to Avalon® Master Bridge Intel FPGA IP RTL Connections
- In the F-Tile PMA/FEC Direct PHY Intel® FPGA IP, disable both the datapath Avalon® interface and the PMA Avalon® interface by unchecking the interfaces as shown in the following figure.
Note: This step is optional. The datapath and PMA Avalon® interface in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP and the Global Avalon® memory-mapped interface can function together.Figure 91. Disable Datapath and PMA Avalon® Interface in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
- Run the Support-Logic Generation for your design in the Intel® Quartus® Prime Pro Edition software and place the F-tile in your design by using the Tile Interface Planner tool as shown in the following figure. Refer to F-tile Interface Planning for more information.
Figure 92. Using Tile Interface Planner to Obtain the F-Tile Co-ordinatesOnce you have the F-tile co-ordinates add the following assignment in your qsf settings file.
set_instance_assignment -name IP_TILE_ASSIGNMENT <F-tile co-ordinates> -to gavmm_inst
For example you must add the following assignment in your qsf settings file for the AGIB027R29A1E2VR0 device.set_instance_assignment -name IP_TILE_ASSIGNMENT Z1577A_X0_Y0_N0 -to gavmm_inst
Note: The gavmm_inst qsf assignment name must be identical to the instance name in your design file or else you can get a placement failure in the design compilation. - To perform hardware testing to access registers using the global Avalon® interface you need to do the following:
- Write the page address of the block you want to access to the page address: 0xffffc. The following table shows the page address of the various blocks in the F-tile.
Table 95. Block and Page Address Block Page Address EMIB 0x00 400G Hard IP 0x02 400G 0x04 200G Hard IP 0x06 200G FEC/PMA Interface 0x08 PCIe Hard IP 0x0A FGT PMA Quad 0 0x0C FGT PMA Quad 1 0x0D FGT PMA Quad 2 0x0E FGT PMA Quad 3 0x0F FHT PMA 0x10 - You can then read and write values to the PMA offset register address to access the registers.
As an example, here are steps to access the registers in a FGT PMA in quad 3 for a one channel 25G design.
- Read address 0xffffc; it should be 0x00000000.
- Write 0xf to address 0xffffc.
- Read address 0xffffc; it should be 0x0000000f.
- Now you can read the various offset address registers to access the register values. In this example, you can read address 0xf0010, 0x40740, and 0x62000 and get their register values.
- Write the page address of the block you want to access to the page address: 0xffffc. The following table shows the page address of the various blocks in the F-tile.