Visible to Intel only — GUID: zej1616508698887
Ixiasoft
Visible to Intel only — GUID: zej1616508698887
Ixiasoft
3.6.4. FGT PMA Fractional Mode
For a given data rate, the drop-down menu lists the supported integer mode reference clock frequencies. For a given data rate, if the required reference clock frequency is not listed in the drop-down, you can either select one of the supported integer mode reference clock frequencies or enable fractional mode.
- When enabling fractional mode, if exact fraction is not available (K = 0.25,0.5, 0.75), use 140MHz reference clock frequency for approximate fractional mode.
- To calculate K, divide k value displayed in the IP GUI system messages; K = k / 2^22. For example, for k = 2097152, K = 0.5.
- For a given data rate, you must enable fractional mode if you need to dynamically configure the K value during run time. When you enable fractional mode, you must enter the TX FGT PLL fractional mode reference clock frequency.
FGT PMA supports fractional mode in following PMA modes:
PMA Mode | Fractional Mode Support |
---|---|
TX simplex | TX FGT PLL supports fractional mode in TX simplex. To enable, select TX simplex option for PMA mode, and turn on the Enable TX FGT PLL fractional mode in the parameter editor. The TX PLL fractional counter values automatically calculate for the selected reference clock frequency. You can place TX Simplex fractional mode on any of 16 FGT TX PMAs.
Note: FGT PMA does not support fractional mode for RX simplex.
|
Duplex | FGT PMA in Duplex PMA mode supports fractional mode. To enable fractional mode in duplex PMA mode, select the Duplex option for PMA mode, select up to 16 for the Number of PMA lanes, and turn on Enable TX FGT PLL fractional mode option in the parameter editor.
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Primary PLL configuration | To enable fractional mode with the primary PLL configuration, select the Duplex option for PMA mode, select 2 or 4 for the Number of PMA lanes, and turn on Enable TX FGT PLL fractional mode and Enable TX FGT PLL cascade mode options in the parameter editor.
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Tuning the Fractional Value in Fractional Mode
You can configure the F-tile FGT PMA to:- Transmit serial data.
- Generate a clock for FPGA core fabric.
You can configure the FGT PMA in fractional mode to adjust the frequency and datarate by a small amount (+/- 1000ppm) for rate matching purposes. Details about how to configure the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for best performance is planned to be included in future user guide releases.
Each FGT PMA has an Avalon® memory-mapped interface register containing the K value. The K value / 2^22 gives the fractional value of the feedback counter. The fractional value plus the M counter value provides the total feedback counter and determines how much PPM each bit in the K value represents.
The procedure to change the K value is:
- Change the K value to the new value.
- Pulse the strobe bit 0 -> 1-> 0 to lock in the new K value.
Each FGT PMA contains 3 PLLs; slow, medium and fast. FGT PMAs are organized in a quad. The K value and strobe bit Avalon® memory-mapped interface register addresses depend on the location of the transceiver in the quad and which PLL is used (slow, medium, fast) as shown in the table below.
Channel Location in Quad | PLL | Fractional K Value Register | Strobe Register |
---|---|---|---|
0 | Slow | 0x44000[30:9] | 0x4400C[17] |
Medium | 0x44100[30:9] | 0x4410C[17] | |
Fast | 0x44200[30:9] | 0x4420C[17] | |
1 | Slow | 0x4C000[30:9] | 0x4C00C[17] |
Medium | 0x4C100[30:9] | 0x4C10C[17] | |
Fast | 0x4C200[30:9] | 0x4C20C[17] | |
2 | Slow | 0x54000[30:9] | 0x5r00C[17] |
Medium | 0x54100[30:9] | 0x5410C[17] | |
Fast | 0x54200[30:9] | 0x5420C[17] | |
3 | Slow | 0x5C000[30:9] | 0x5C00C[17] |
Medium | 0x5C100[30:9] | 0x5C10C[17] | |
Fast | 0x5C200[30:9] | 0x5C20C[17] |
; z1577a_u_ux_quad_3__ux3_synth_lc_med_en ; enable ; String ;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_f_out_hz ; 0000000001010110011011010011111010000000 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_f_pfd_hz ; 0000000000000000000000000000000000000000 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_f_ref_hz ; 0000000000001000110110011110111000100000 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_f_rx_postdiv_hz ; 0000000000010001010010010000110010000000 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_f_tx_postdiv_hz ; 0000000000000110111010100000010100000000 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_f_vco_hz ; 0000001010110011011010011111010000000000 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_fractional_en ; enable ; String ;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_k_counter ; 0000111010100111001110 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_l_counter ; 001000 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_m_counter ; 000100111 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_n_counter ; 000001 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_powerdown_mode ; false ; String ;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_primary_use ; ux3_synth_lc_med_primary_use_disabled ; String ;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_rx_postdiv_counter ; 00101000 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_tx_postdiv_counter ; 01100100 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_tx_postdiv_fractional_en ; disable ; String ;