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1. F-tile Overview
2. F-tile Architecture
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP
5. Implementing the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP
6. F-tile PMA/FEC Direct PHY Design Implementation
7. Supported Tools
8. Debugging F-Tile Transceiver Links
9. F-tile Architecture and PMA and FEC Direct PHY IP User Guide Archives
10. Document Revision History for F-tile Architecture and PMA and FEC Direct PHY IP User Guide
2.1.1. FHT and FGT PMAs
2.1.2. 400G Hard IP and 200G Hard IP
2.1.3. PMA Data Rates
2.1.4. FEC Architecture
2.1.5. PCIe* Hard IP
2.1.6. Bonding Architecture
2.1.7. Deskew Logic
2.1.8. Embedded Multi-die Interconnect Bridge (EMIB)
2.1.9. IEEE 1588 Precision Time Protocol for Ethernet
2.1.10. Clock Networks
2.1.11. Reconfiguration Interfaces
2.2.1. PMA-to-Fracture Mapping
2.2.2. Determining Which PMA to Map to Which Fracture
2.2.3. Hard IP Placement Rules
2.2.4. IEEE 1588 Precision Time Protocol Placement Rules
2.2.5. Topologies
2.2.6. FEC Placement Rules
2.2.7. Clock Rules and Restrictions
2.2.8. Bonding Placement Rules
2.2.9. Preserving Unused PMA Lanes
2.2.2.1. Implementing One 200GbE-4 Interface with 400G Hard IP and FHT
2.2.2.2. Implementing One 200GbE-2 Interface with 400G Hard IP and FHT
2.2.2.3. Implementing One 100GbE-1 Interface with 400G Hard IP and FHT
2.2.2.4. Implementing One 100GbE-4 Interface with 400G Hard IP and FGT
2.2.2.5. Implementing One 10GbE-1 Interface with 200G Hard IP and FGT
2.2.2.6. Implementing Three 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.7. Implementing One 50GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.8. Implementing One 100GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.9. Implementing Two 100GbE-1 and One 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.10. Implementing 100GbE-1, 100GbE-2, and 50GbE-1 Interfaces with 400G Hard IP and FHT
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview
3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP
3.3. Configuring the IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting Reset
3.9. Bonding Implementation
3.10. Independent Port Configurations
3.11. Configuration Registers
3.12. Configurable Intel® Quartus® Prime Software Settings
3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. RS-FEC Signals
3.4.5. Custom Cadence Control and Status Signals
3.4.6. TX PMA Status Signals
3.4.7. RX PMA Status Signals
3.4.8. TX and RX PMA and Core Interface FIFO Signals
3.4.9. PMA Avalon® Memory Mapped Interface Signals
3.4.10. Datapath Avalon® Memory Mapped Interface Signals
3.5.1. Parallel Data Mapping Information
3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations
3.5.3. Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1)
3.5.4. Example of TX Parallel Data for PMA width = 64 (X=2)
3.5.5. Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Reset Signals—Descriptions
3.8.5. Status Signals—Descriptions
3.8.6. Run-time Reset Sequence—TX
3.8.7. Run-time Reset Sequence—RX
3.8.8. Run-time Reset Sequence—TX + RX
3.8.9. Run-time Reset Sequence—TX with FEC
6.1. Implementing the F-tile PMA/FEC Direct PHY Design
6.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
6.3. Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
6.4. Instantiating the F-Tile Reference and System PLL Clocks Intel® FPGA IP
6.5. Enabling Custom Cadence Generation Ports and Logic
6.6. Connecting the F-tile PMA/FEC Direct PHY Design IP
6.7. Simulating the F-Tile PMA/FEC Direct PHY Design
6.8. F-tile Interface Planning
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3.3.3.1. RX FGT PMA Interface Options
Figure 63. RX FGT PMA Interface Options in Parameter Editor
Parameter | Values | Description |
---|---|---|
RX FGT PMA Parameters | ||
RX PMA interface FIFO mode | Register Elastic |
Selects the RX PMA Interface FIFO mode. Default value is Elastic. |
Enable rx_pmaif_fifo_empty port | On/Off | Enables the port that indicates the RX PMA Interface FIFO's empty condition. Default value is Off. |
Enable rx_pmaif_fifo_pempty port | On/Off | Enables the port that indicates the RX PMA Interface FIFO's partially empty condition. Default value is Off. |
Enable rx_pmaif_fifo_pfull port | On/Off | Enables the port that indicates the RX PMA Interface FIFO's partially full condition. Default value is Off. |
RX Core Interface Parameters | ||
RX core interface FIFO mode | Phase compensation Elastic |
Specifies the mode for the RX Core Interface FIFO. Default value is Phase compensation. |
Enable RX double width transfer | On/Off | Enables double width RX data transfer mode. In this mode, core logic can be clocked with a half rate clock. Default value is On. |
RX core interface FIFO partially full threshold | 10 | Specifies the partially full threshold for the RX Core Interface FIFO. Default value is 10. |
RX core interface FIFO partially empty threshold | 2 | Specifies the partially empty threshold for the RX Core Interface FIFO. Default value is 2. |
Enable rx_fifo_full port | On/Off | Enables the optional rx_fifo_full status output port. This signal indicates when the RX core FIFO has reached the full threshold. This signal is synchronous with rx_clkout. Default value is Off. |
Enable rx_fifo_empty port | On/Off | Enables the optional rx_fifo_empty status output port. This signal indicates when the RX core FIFO has reached the empty threshold. This signal is synchronous with rx_clkout. Default value is Off. |
Enable rx_fifo_pfull port | On/Off | Enables the optional rx_fifo_pfull status output port. This signal indicates when the RX core FIFO has reached the specified partially full threshold. Default value is Off. |
Enable rx_fifo_pempty port | On/Off | Enables the optional rx_fifo_pempty status output port. This signal indicates when the RX core FIFO has reached the specified partially empty threshold. Default value is Off. |
Enable rx_fifo_rd_en port | On/Off | Enables the optional rx_fifo_rd_en control input port. This port is used for Elastic FIFO mode. Asserting this signal enables the read from RX core FIFO. You must enable this read enable when using Elastic FIFO. Default value is Off. |
RX Clock Options | ||
Selected rx_clkout clock source | Word Clock Bond Clock User Clock 1 User Clock 2 Sys PLL Clock Sys PLL Clock Div2 |
Specifies the rx_clkout output port source. Default value is Sys PLL Clock Div2. |
Frequency of rx_clkout | Output | Displays the frequency of rx_clkout in MHz based on rx_clkout source selection. |
Enable rx_clkout2 port | On/Off | Enables the optional rx_clkout2 output clock. Default value is Off. |
Selected rx_clkout2 clock source | Word Clock Bond Clock User Clock 1 User Clock 2 Sys PLL Clock Sys PLL Clock Div2 |
Specifies the rx_clkout output port source. Default value is Word Clock. |
rx_clkout2 clock div by | 1, 2 | Selects the rx_clkout2 divider setting that divides out the rx_clkout2 output port source. Default value is 1. |
Frequency of rx_clkout2 | Output | Displays the frequency of rx_clkout2 in MHz based on rx_clkout2 source selection and rx_clkout2 clock divide by factor. |
Selected rx_coreclkin clock network | Dedicated Clock Global Clock |
Specifies the type of clock network to use to route the clock signal to rx_coreclkin port. Dedicated Clock allows a higher maximum frequency (fmax) between the FPGA fabric and the FPGA fabric and RX Core interface FIFO. The number of Dedicated Clock lines are limited. Default value is Dedicated Clock. |