Visible to Intel only — GUID: nqy1613492617491
Ixiasoft
5.1. Clock Signals
5.2. Reset Signals
5.3. TX MII Interface (64b/66b)
5.4. RX MII Interface (64b/66b)
5.5. Status Interface for 64b/66b Line Rate
5.6. TX Interface (8b/10b)
5.7. RX Interface (8b/10b)
5.8. Status Interface for 8b/10b Line Rate
5.9. Serial Interface
5.10. CPRI PHY Reconfiguration Interface
5.11. Datapath Avalon Memory-Mapped Interface
5.12. PMA Avalon Memory-Mapped Interface
Visible to Intel only — GUID: nqy1613492617491
Ixiasoft
1. About the F-Tile CPRI PHY Intel® FPGA IP Core
Updated for: |
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Intel® Quartus® Prime Design Suite 22.1 |
IP Version 3.2.0 |
The F-Tile CPRI PHY Intel® FPGA IP core implements the physical layer (layer 1) specification in the Intel® Agilex™ devices based on the Common Public Radio Interface (CPRI) v7.0 Specification (2015-10-09).