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1. F-tile Overview
2. F-tile Architecture
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP
5. Implementing the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP
6. F-tile PMA/FEC Direct PHY Design Implementation
7. Supported Tools
8. Debugging F-Tile Transceiver Links
9. F-tile Architecture and PMA and FEC Direct PHY IP User Guide Archives
10. Document Revision History for F-tile Architecture and PMA and FEC Direct PHY IP User Guide
2.1.1. FHT and FGT PMAs
2.1.2. 400G Hard IP and 200G Hard IP
2.1.3. PMA Data Rates
2.1.4. FEC Architecture
2.1.5. PCIe* Hard IP
2.1.6. Bonding Architecture
2.1.7. Deskew Logic
2.1.8. Embedded Multi-die Interconnect Bridge (EMIB)
2.1.9. IEEE 1588 Precision Time Protocol for Ethernet
2.1.10. Clock Networks
2.1.11. Reconfiguration Interfaces
2.2.1. PMA-to-Fracture Mapping
2.2.2. Determining Which PMA to Map to Which Fracture
2.2.3. Hard IP Placement Rules
2.2.4. IEEE 1588 Precision Time Protocol Placement Rules
2.2.5. Topologies
2.2.6. FEC Placement Rules
2.2.7. Clock Rules and Restrictions
2.2.8. Bonding Placement Rules
2.2.9. Preserving Unused PMA Lanes
2.2.2.1. Implementing One 200GbE-4 Interface with 400G Hard IP and FHT
2.2.2.2. Implementing One 200GbE-2 Interface with 400G Hard IP and FHT
2.2.2.3. Implementing One 100GbE-1 Interface with 400G Hard IP and FHT
2.2.2.4. Implementing One 100GbE-4 Interface with 400G Hard IP and FGT
2.2.2.5. Implementing One 10GbE-1 Interface with 200G Hard IP and FGT
2.2.2.6. Implementing Three 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.7. Implementing One 50GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.8. Implementing One 100GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.9. Implementing Two 100GbE-1 and One 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.10. Implementing 100GbE-1, 100GbE-2, and 50GbE-1 Interfaces with 400G Hard IP and FHT
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview
3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP
3.3. Configuring the IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting Reset
3.9. Bonding Implementation
3.10. Independent Port Configurations
3.11. Configuration Registers
3.12. Configurable Intel® Quartus® Prime Software Settings
3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. RS-FEC Signals
3.4.5. Custom Cadence Control and Status Signals
3.4.6. TX PMA Status Signals
3.4.7. RX PMA Status Signals
3.4.8. TX and RX PMA and Core Interface FIFO Signals
3.4.9. PMA Avalon® Memory Mapped Interface Signals
3.4.10. Datapath Avalon® Memory Mapped Interface Signals
3.5.1. Parallel Data Mapping Information
3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations
3.5.3. Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1)
3.5.4. Example of TX Parallel Data for PMA width = 64 (X=2)
3.5.5. Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Reset Signals—Descriptions
3.8.5. Status Signals—Descriptions
3.8.6. Run-time Reset Sequence—TX
3.8.7. Run-time Reset Sequence—RX
3.8.8. Run-time Reset Sequence—TX + RX
3.8.9. Run-time Reset Sequence—TX with FEC
6.1. Implementing the F-tile PMA/FEC Direct PHY Design
6.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
6.3. Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
6.4. Instantiating the F-Tile Reference and System PLL Clocks Intel® FPGA IP
6.5. Enabling Custom Cadence Generation Ports and Logic
6.6. Connecting the F-tile PMA/FEC Direct PHY Design IP
6.7. Simulating the F-Tile PMA/FEC Direct PHY Design
6.8. F-tile Interface Planning
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Ixiasoft
8.3. Transceiver Toolkit Parameter Settings
The following table describes the transceiver toolkit parameter settings.
Parameter | Description | Control Pane | |
---|---|---|---|
Auto refresh RX CDR status | Enable this option to update the RX CDR status real time. | Receiver pane. | |
Auto refresh RX PMA settings | Enable this option to update the RX Equalization settings real time for FGT PMA. | Receiver pane. | |
Auto refresh TX Status | Enable this option to update the TX PLL lock status real time. | Transmitter pane | |
Bit error rate (BER) | Reports the number of errors divided by bits tested since the last reset of the checker. When RX CDR is locked to reference clock or PRBS checker is not locked, the BER reported is not reliable. | Receiver pane | |
Clear Stats | Clear the current number of bits tested, number of error bits and BER. | Receiver pane | |
Hard PRBS checker running | Red: checker stops. Green: checker is checking, and data pattern is locked. |
Receiver pane | |
Hard PRBS generator running | Red: generator stops. Green: generator is sending a pattern. |
Transmitter pane | |
Inject Error | Inject a bit error in the transmitter PRBS pattern. | Transmitter pane | |
Line encoding | Specifies the modulation type used for serial data. | Transmitter and receiver pane | |
Loopback mode | Select the loopbacks mode. The available options are:
|
Transmitter and receiver pane | |
Number of bits tested | Specifies the number of bits tested since the last reset of the checker. When RX CDR is locked to reference clock or PRBS checker is not locked, the BER reported is not reliable | Receiver pane | |
Number of error bits | Specifies the number of error bits encountered since the last reset of the checker. When RX CDR is locked to reference clock or PRBS checker is not locked, the BER reported is not reliable | Receiver pane | |
PRBS locked | Green: indicates the PRBS checker is locked to the received PRBS pattern. | Receiver pane | |
PRBS pattern | Select the test pattern for the bit error test. | Transmitter and receiver pane | |
RX CDR locked to ref clock | Green: Indicates the receiver in lock-to-reference (LTR) mode. | Receiver pane | |
RX CDR locked to data | Green: Indicates the receiver in lock-to-data (LTD) mode. | Receiver pane | |
RX Enable Gray Code | Enables Gray coding for PAM4 only. | Receiver pane | |
RX PMA Settings | RX Equalization settings. | Receiver pane | |
RX Polarity Inversion | Enable RX polarity inversion. | Receiver pane | |
RX Ready | Green: RX channel out of reset. | Receiver pane | |
RX Reset FGT PMA | Reset the FGT RX datapath.
Note: Clicking the RX reset of one channel resets all the RX channels in the same F-Tile PMA/FEC Direct PHY Intel® FPGA IP instance.
|
Receiver pane | |
Start | Starts the pattern generator or checker on the channel to verify incoming data. | Transmitter and receiver pane | |
Stop | Stops generating patterns and testing the channel. | Transmitter and receiver pane | |
TX Enable Gray Code | Enables Gray coding for PAM4 only. | Transmitter pane | |
TX Equalization Parameters | FGT 41 | FHT 42 43 | Transmitter pane and receiver pane |
M1: Post-cursor 1 C0: Main cursor P1: Pre-cursor 1 P2: Pre-cursor 2 |
M3: Pre-cursor 3 M2: Pre-cursor 2 M1: Pre-cursor 1 C0: Main cursor P1: Post-cursor 1 P2: Post-cursor 2 P3: Post-cursor 3 P4: Post-cursor 4 |
||
TX PLL Locked | Green: Indicates TX PLL locks to reference clock. | Transmitter pane | |
TX Polarity Inversion | Enable TX polarity inversion. | Transmitter pane | |
TX Reset FGT PMA | Reset the FGT TX PMA datapath.
Note: Clicking the TX reset of one channel resets all the TX channels in the same F-Tile PMA/FEC Direct PHY Intel® FPGA IP instance.
|
Transmitter pane |
Related Information
41 Refer to F-Tile TX Equalizer Tool for legal settings.
42 Refer to FHT PMA Architecture for legal settings.
43 When internal serial loopback is enabled, the TX Equalization Parameters are set to default values.