Visible to Intel only — GUID: vkk1627517017814
Ixiasoft
1. F-tile Overview
2. F-tile Architecture
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP
5. Implementing the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP
6. F-tile PMA/FEC Direct PHY Design Implementation
7. Supported Tools
8. Debugging F-Tile Transceiver Links
9. F-tile Architecture and PMA and FEC Direct PHY IP User Guide Archives
10. Document Revision History for F-tile Architecture and PMA and FEC Direct PHY IP User Guide
2.1.1. FHT and FGT PMAs
2.1.2. 400G Hard IP and 200G Hard IP
2.1.3. PMA Data Rates
2.1.4. FEC Architecture
2.1.5. PCIe* Hard IP
2.1.6. Bonding Architecture
2.1.7. Deskew Logic
2.1.8. Embedded Multi-die Interconnect Bridge (EMIB)
2.1.9. IEEE 1588 Precision Time Protocol for Ethernet
2.1.10. Clock Networks
2.1.11. Reconfiguration Interfaces
2.2.1. PMA-to-Fracture Mapping
2.2.2. Determining Which PMA to Map to Which Fracture
2.2.3. Hard IP Placement Rules
2.2.4. IEEE 1588 Precision Time Protocol Placement Rules
2.2.5. Topologies
2.2.6. FEC Placement Rules
2.2.7. Clock Rules and Restrictions
2.2.8. Bonding Placement Rules
2.2.9. Preserving Unused PMA Lanes
2.2.2.1. Implementing One 200GbE-4 Interface with 400G Hard IP and FHT
2.2.2.2. Implementing One 200GbE-2 Interface with 400G Hard IP and FHT
2.2.2.3. Implementing One 100GbE-1 Interface with 400G Hard IP and FHT
2.2.2.4. Implementing One 100GbE-4 Interface with 400G Hard IP and FGT
2.2.2.5. Implementing One 10GbE-1 Interface with 200G Hard IP and FGT
2.2.2.6. Implementing Three 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.7. Implementing One 50GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.8. Implementing One 100GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.9. Implementing Two 100GbE-1 and One 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.10. Implementing 100GbE-1, 100GbE-2, and 50GbE-1 Interfaces with 400G Hard IP and FHT
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview
3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP
3.3. Configuring the IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting Reset
3.9. Bonding Implementation
3.10. Independent Port Configurations
3.11. Configuration Registers
3.12. Configurable Intel® Quartus® Prime Software Settings
3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. RS-FEC Signals
3.4.5. Custom Cadence Control and Status Signals
3.4.6. TX PMA Status Signals
3.4.7. RX PMA Status Signals
3.4.8. TX and RX PMA and Core Interface FIFO Signals
3.4.9. PMA Avalon® Memory Mapped Interface Signals
3.4.10. Datapath Avalon® Memory Mapped Interface Signals
3.5.1. Parallel Data Mapping Information
3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations
3.5.3. Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1)
3.5.4. Example of TX Parallel Data for PMA width = 64 (X=2)
3.5.5. Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Reset Signals—Descriptions
3.8.5. Status Signals—Descriptions
3.8.6. Run-time Reset Sequence—TX
3.8.7. Run-time Reset Sequence—RX
3.8.8. Run-time Reset Sequence—TX + RX
3.8.9. Run-time Reset Sequence—TX with FEC
6.1. Implementing the F-tile PMA/FEC Direct PHY Design
6.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
6.3. Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
6.4. Instantiating the F-Tile Reference and System PLL Clocks Intel® FPGA IP
6.5. Enabling Custom Cadence Generation Ports and Logic
6.6. Connecting the F-tile PMA/FEC Direct PHY Design IP
6.7. Simulating the F-Tile PMA/FEC Direct PHY Design
6.8. F-tile Interface Planning
Visible to Intel only — GUID: vkk1627517017814
Ixiasoft
3.14.1.3. TX Equalizer Settings
The TX equalizer settings provides a way to tune your PMA TX buffer to optimize link performance.
To update the TX equalizer settings, follow these steps:
- Set csr_txffe_coeff_load (0x45080[0]) to 1’b0.
- Set TX equalizer co-efficients to valid settings:
- TX equalizer pre-cursor 3 register csr_txffe_coeff_p5(0x45084[23:18]).
- TX equalizer pre-cursor 2 register csr_txffe_coeff_m2(0x45080[7:2]).
- TX equalizer pre-cursor 1 register csr_txffe_coeff_m1(0x45080[13:8]).
- TX equalizer main cursor register csr_txffe_coeff_0(0x45080[20:14]).
- TX equalizer post-cursor 1 register csr_txffe_coeff_p1(0x45080[26:21]).
- TX equalizer post-cursor 2 register csr_txffe_coeff_p2(0x45084[5:0]).
- TX equalizer post-cursor 3 register csr_txffe_coeff_p3(0x45084[11:6])
- TX equalizer post-cursor 4 register csr_txffe_coeff_p4(0x45084[17:12]).
- Toggle csr_txffe_coeff_load (0x45080[0]) to 1’b1 and back to 1’b0.
Note: For the range of TX PMA equalizer parameters, refer to FHT Transmitter PMA Equalizer Parameters for NRZ and PAM4 Modes.
Table 86. Main Cursor (C0) Real Co-efficient Values Main Cursor (C0) – Register 0x45080[20:14] Settings (decimal)
Real Co-efficient Values 0 0 1 0.5 2 1 … … 82 41 83 41.5 Table 87. Pre-Cursor (C-1) and Post-Cursor (C1) Real Co-efficient Values Pre-Cursor (C-1) – Register 0x45080[13:8]
Post-Cursor (C1) – Register 0x45080[26:21]
Settings (decimal)
Real Co-efficient Values 0 0 1 0.5 2 1 … … 30 15 31 15.5 32 -16 33 -15.5 … … 62 -1 63 -0.5 Table 88. Pre-Cursor (C-2, C-3) and Post-Cursor (C2, C3, C4) Real Co-efficient Values Pre-Cursor (C-2) – Register 0x45080 [7:2]
Pre-Cursor (C-3) – Register 0x45084[23:18]
Post-Cursor (C2) – Register 0x45084[5:0]
Post-Cursor (C3) – Register 0x45084[11:6]
Post-Cursor (C4) – Register 0x45084[17:12]
Settings (decimal)
Real Co-efficient Values 0 0 1 0.25 2 0.5 … … 30 7.5 31 7.75 32 -8 33 -7.75 … … 62 -0.5 63 -0.25