Visible to Intel only — GUID: dzk1615854161921
Ixiasoft
Visible to Intel only — GUID: dzk1615854161921
Ixiasoft
6.1. Implementing the F-tile PMA/FEC Direct PHY Design
This design implementation requires the following IP available from the Intel® Quartus® Prime Pro Edition software IP Catalog:
- F-Tile PMA/FEC Direct PHY Intel® FPGA IP
- F-Tile Reference and System PLL Clocks Intel® FPGA IP
The F-Tile PMA/FEC Direct PHY Intel® FPGA IP is the primary IP component for PMA and FEC direct implementation. This IP provides direct access to the F-tile PMA block features for both FGT and FHT.
To customize and instantiate the IP for your protocol implementation, you specify parameter values for the F-Tile PMA/FEC Direct PHY Intel® FPGA IP and generate the IP RTL and supporting files from the Intel® Quartus® Prime parameter editor.
The top-level file generated with the IP instance includes all the available ports for your configuration. You use these ports to connect the F-Tile PMA/FEC Direct PHY Intel® FPGA IP to other IP components in your design. These include connections to the respective reference clock pins and system PLL clock outputs from the F-Tile Reference and System PLL Clocks Intel® FPGA IP, TX and RX parallel data ports, as well as TX and RX serial data pins.
F-tile PMA/FEC Direct PHY Design IP Connections shows the connections between the IP design blocks required for the F-tile PMA/FEC Direct PHY design. The diagram illustrates the connections between the F-Tile Reference and System PLL Clocks Intel® FPGA IP, the Soft Reset Controller (that instantiates automatically after running Design Analysis), and the user-provided MAC/PCS IP core into the parallel data bus to the F-Tile PMA/FEC Direct PHY Intel® FPGA IP.
The following topics describe PHY IP parameterization, connection, simulation, and tile placement planning for the design:
- Instantiating the F-Tile PMA/FEC Direct PHY Intel FPGA IP
- Instantiating the F-Tile Reference and System PLL Clocks Intel FPGA IP
- Enabling Custom Cadence Generation Ports and Logic
- Connecting the F-tile PMA/FEC Direct PHY Design IP
- Simulating the F-Tile PMA/FEC Direct PHY Design
- F-tile Interface Planning