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Ixiasoft
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Ixiasoft
2.2.5. Topologies
F-tile-supported protocols use EMIBs, PMAs, and streams for the relevant hard IP. Because hard IPs in multi-protocol F-tile designs share PMAs and EMIBs, specific pairings of PMAs and EMIBs are required to support different combinations of hard IPs, PTP-enabled ports, and bandwidths. These pairings are called topologies. F-tile supports 15 pre-defined topologies, each with different constraints. Every F-tile design must follow one of these topologies. You cannot dynamically reconfigure from one topology to another. Dynamic reconfiguration is allowed only within a topology.
Select a topology based on the following design considerations:
- Do you need PCIe* ?
- Do you need IEEE 1588 precision time protocol ports?
- Do you need FHT PMA lanes?
If you need to implement multiple hard IPs, verify that there is a topology that meets your requirements.
- If your F-tile design does not utilize all tile resources, there may be more than one topology that meets your requirements.
- If more than one topology meets your requirements, select the topology with the most PMAs and streams available to ensure that the maximum number of hard IPs can be implemented.
- Use the F-Tile Channel Placement Tool to plan your design; it shows available PMA, stream, and EMIB locations for each topology.
Topology | PCIe* Hard IP | 400G Hard IP | 200G Hard IP | |||||||
---|---|---|---|---|---|---|---|---|---|---|
Avail-ability | Config-uration | Avail-ability | Configuration | Avail-ability | Configuration 4 | |||||
PMA | PTP | Number of PMAs | Number of Streams | Number of PMAs | Number of Streams | |||||
1 | Yes | 1x PCIe* x16 | No | N/A | N/A | N/A | N/A | No | N/A | N/A |
2 | Yes | 2x PCIe* x8 | No | N/A | N/A | N/A | N/A | No | N/A | N/A |
3 | Yes | 1x PCIe* x16 | Yes | FHT | Yes | 4 | 4 | No | N/A | N/A |
4 | Yes | 4x PCIe* x4 | No | N/A | N/A | N/A | N/A | No | N/A | N/A |
5 | No | N/A | Yes | FHT | No | 4 | 16 | Yes | 8 | 8 |
6 | No | N/A | Yes | FHT | Yes | 4 | 16 | Yes | 6 | 6 |
7 | Yes | 1x PCIe* x4 | Yes | FHT | Yes | 4 | 16 | No | N/A | N/A |
8 | Yes | 1x PCIe* x8 | Yes | FHT | Yes | 4 | 10 | No | N/A | N/A |
9 | Yes | 2x PCIe* x4 | Yes | FHT | Yes | 4 | 10 | No | N/A | N/A |
10 | No | N/A | Yes | FGT | No | 8 | 16 | Yes | 8 | 8 |
11 | No | N/A | Yes | FGT | Yes | 8 | 16 | Yes | 6 | 6 |
12 | Yes | 1x PCIe* x8 | Yes | FGT | Yes | 8 | 11 | No | N/A | N/A |
13 | Yes | 2x PCIe* x4 | Yes | FGT | Yes | 8 | 11 | No | N/A | N/A |
14 | Yes | 1x PCIe* x4 | Yes | FGT | Yes | 8 | 16 | No | N/A | N/A |
15 | No | N/A | Yes | FGT | Yes | 16 | 16 | No | N/A | N/A |
For example, in Topology 2: 2x PCIe x8 :
- The PCIe* hard IP implements two ports of PCIe* x8.
- You cannot implement any other protocol interface in this F-tile.
- 400G hard IP and 200G hard IP are unavailable.
Topology 3: 1x PCIe x16 + 400G Hard IP (FHT) with PTP is a superset of Topology 1: 1x PCIe x16 . That means that, if your target implementation works with Topology 1: 1x PCIe x16 , it also works with Topology 3: 1x PCIe x16 + 400G Hard IP (FHT) with PTP .
- Topology 5: 400G Hard IP (FHT) + 200G Hard IP (FGT) Example
- Topology 14: 1x PCIe x4 + 400G Hard IP (FGT) with PTP Example