Visible to Intel only — GUID: jna1614265934814
Ixiasoft
Visible to Intel only — GUID: jna1614265934814
Ixiasoft
3.6.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source
Recommended Connection and Source shows recommended tx/rx_coreclkin connection and tx/rx_clkout and tx/rx_clkout2 source, based on the datapath clocking mode and double-width transfer selection.
Datapath Clocking Mode | Core Interface FIFO Mode | Enable TX/RX Double Width Transfer | Recommended tx/rx_coreclkin connection | Recommended tx/rx_clkout/2 or tx/rx_clkout2 source | Division factor if tx/rx_clkout2 |
---|---|---|---|---|---|
PMA | PC | No | tx/rx_clkout | Word/Bond clock | N/A |
Yes | tx/rx_clkout2 | Word/Bond clock | 2 | ||
Elastic | Yes | tx/rx_clkout2 or any other clock source from user | Word/Bond clock/User clock1 or 2 | 2 | |
No | tx/rx_clkout or any other clock source from user | Word/Bond clock/User clock1 or 2 | N/A | ||
System PLL | PC | No | tx/rx_clkout | Sys PLL clock | N/A |
Yes | tx/rx_clkout | Sys PLL clock Div2 | N/A |
- When using system PLL clocking mode, both tx_clkout and rx_clkout can clock tx_coreclk_in and rx_coreclk_in.
-
When using PMA clocking mode, tx_cllkout/2 must clock tx_coreclk_in. rx_clkout/2 must clock rx_coreclk_in. The only exception to this requirement in PMA clocking mode is for chip to chip applications where TX and RX share same reference clock source (that is, 0 PPM difference), tx_clkout or rx_clkout can clock both tx_coreclk_in and rx_coreclk.