F-tile Architecture and PMA and FEC Direct PHY IP User Guide

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ID 683872
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. F-tile Overview 2. F-tile Architecture 3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP 5. Implementing the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP 6. F-tile PMA/FEC Direct PHY Design Implementation 7. Supported Tools 8. Debugging F-Tile Transceiver Links 9. F-tile Architecture and PMA and FEC Direct PHY IP User Guide Archives 10. Document Revision History for F-tile Architecture and PMA and FEC Direct PHY IP User Guide
2. F-tile Architecture x
2.1. F-Tile Building Blocks 2.2. F-Tile Placement Rules 2.3. PMA Architecture 2.4. Clock Architecture
2.1. F-Tile Building Blocks x
2.1.1. FHT and FGT PMAs 2.1.2. 400G Hard IP and 200G Hard IP 2.1.3. PMA Data Rates 2.1.4. FEC Architecture 2.1.5. PCIe* Hard IP 2.1.6. Bonding Architecture 2.1.7. Deskew Logic 2.1.8. Embedded Multi-die Interconnect Bridge (EMIB) 2.1.9. IEEE 1588 Precision Time Protocol for Ethernet 2.1.10. Clock Networks 2.1.11. Reconfiguration Interfaces
2.2. F-Tile Placement Rules x
2.2.1. PMA-to-Fracture Mapping 2.2.2. Determining Which PMA to Map to Which Fracture 2.2.3. Hard IP Placement Rules 2.2.4. IEEE 1588 Precision Time Protocol Placement Rules 2.2.5. Topologies 2.2.6. FEC Placement Rules 2.2.7. Clock Rules and Restrictions 2.2.8. Bonding Placement Rules 2.2.9. Preserving Unused PMA Lanes
2.2.1. PMA-to-Fracture Mapping x
2.2.1.1. FHT-PMA-to-400G-Hard-IP-Fracture Mapping 2.2.1.2. FGT-PMA-to-400G-Hard-IP-Fracture Mapping 2.2.1.3. FGT-PMA-to-200G-Hard-IP-Fracture Mapping
2.2.2. Determining Which PMA to Map to Which Fracture x
2.2.2.1. Implementing One 200GbE-4 Interface with 400G Hard IP and FHT 2.2.2.2. Implementing One 200GbE-2 Interface with 400G Hard IP and FHT 2.2.2.3. Implementing One 100GbE-1 Interface with 400G Hard IP and FHT 2.2.2.4. Implementing One 100GbE-4 Interface with 400G Hard IP and FGT 2.2.2.5. Implementing One 10GbE-1 Interface with 200G Hard IP and FGT 2.2.2.6. Implementing Three 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.7. Implementing One 50GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.8. Implementing One 100GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.9. Implementing Two 100GbE-1 and One 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.10. Implementing 100GbE-1, 100GbE-2, and 50GbE-1 Interfaces with 400G Hard IP and FHT
2.2.5. Topologies x
2.2.5.1. Topology 5: 400G Hard IP (FHT) + 200G Hard IP (FGT) Example 2.2.5.2. Topology 14: 1x PCIe x4 + 400G Hard IP (FGT) with PTP Example
2.2.8. Bonding Placement Rules x
2.2.8.1. Bonded Lanes Use Case 1 2.2.8.2. Bonded Lanes Use Case 2
2.3. PMA Architecture x
2.3.1. FHT PMA Architecture 2.3.2. FGT PMA Architecture
2.3.1. FHT PMA Architecture x
2.3.1.1. FHT Transmitter PMA Architecture 2.3.1.2. FHT Receiver PMA Architecture 2.3.1.3. FHT PMA Loopback Modes
2.3.1.1. FHT Transmitter PMA Architecture x
2.3.1.1.1. FHT Transmitter Buffer and Phase Generator 2.3.1.1.2. FHT Serializer 2.3.1.1.3. FHT Gray-Coder and Pre-Coder 2.3.1.1.4. FHT Data Pattern Generator and Verifier
2.3.1.2. FHT Receiver PMA Architecture x
2.3.1.2.1. FHT Receiver Buffer and Equalizer 2.3.1.2.2. CDR Block 2.3.1.2.3. FHT Deserializer
2.3.2. FGT PMA Architecture x
2.3.2.1. FGT Transmitter PMA Architecture 2.3.2.2. FGT Receiver PMA Architecture 2.3.2.3. FGT PMA Tuning 2.3.2.4. FGT PMA Loopback Modes
2.3.2.1. FGT Transmitter PMA Architecture x
2.3.2.1.1. FGT Transmitter Buffer and Phase Generator 2.3.2.1.2. FGT Serializer 2.3.2.1.3. FGT Gray-Coder and Pre-Coder 2.3.2.1.4. FGT Data Pattern Generator and Verifier
2.3.2.2. FGT Receiver PMA Architecture x
2.3.2.2.1. FGT Receiver Buffer and Equalizer 2.3.2.2.2. Control Unit 2.3.2.2.3. FGT Deserializer
2.4. Clock Architecture x
2.4.1. Reference Clock Network 2.4.2. Datapath Clock Network 2.4.3. System PLL 2.4.4. Datapath Clock Cadences
2.4.1. Reference Clock Network x
2.4.1.1. FHT Reference Clock Network 2.4.1.2. FGT and System PLL Reference Clock Network 2.4.1.3. FGT Primary PLL Configuration
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview 3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP 3.3. Configuring the IP 3.4. Signal and Port Reference 3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath 3.6. Clocking 3.7. Custom Cadence Generation Ports and Logic 3.8. Asserting Reset 3.9. Bonding Implementation 3.10. Independent Port Configurations 3.11. Configuration Registers 3.12. Configurable Intel® Quartus® Prime Software Settings 3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing 3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview x
3.1.1. PMA Direct Supported Modes 3.1.2. FEC Direct Supported Modes 3.1.3. Unsupported PMA/FEC Modes
3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.2.1. Preset IP Parameter Settings
3.3. Configuring the IP x
3.3.1. General and Common Datapath Options 3.3.2. TX Datapath Options 3.3.3. RX Datapath Options 3.3.4. RS-FEC (Reed Solomon Forward Error Correction) Options 3.3.5. Avalon® Memory Mapped Interface Options 3.3.6. Example Design Generation
3.3.2. TX Datapath Options x
3.3.2.1. TX PMA interface Parameters
3.3.3. RX Datapath Options x
3.3.3.1. RX FGT PMA Interface Options
3.4. Signal and Port Reference x
3.4.1. TX and RX Parallel and Serial Interface Signals 3.4.2. TX and RX Reference Clock and Clock Output Interface Signals 3.4.3. Reset Signals 3.4.4. RS-FEC Signals 3.4.5. Custom Cadence Control and Status Signals 3.4.6. TX PMA Status Signals 3.4.7. RX PMA Status Signals 3.4.8. TX and RX PMA and Core Interface FIFO Signals 3.4.9. PMA Avalon® Memory Mapped Interface Signals 3.4.10. Datapath Avalon® Memory Mapped Interface Signals
3.4.10. Datapath Avalon® Memory Mapped Interface Signals x
3.4.10.1. Number of Datapath Memory Mapped Avalon® Interfaces and Additional Address Bits per Interface
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath x
3.5.1. Parallel Data Mapping Information 3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations 3.5.3. Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1) 3.5.4. Example of TX Parallel Data for PMA width = 64 (X=2) 3.5.5. Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode
3.6. Clocking x
3.6.1. Clock Ports 3.6.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source 3.6.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2 3.6.4. FGT PMA Fractional Mode 3.6.5. FGT Core PLL Mode
3.7. Custom Cadence Generation Ports and Logic x
3.7.1. Enabling the tx_cadence_slow_clk_locked Port 3.7.2. Rate Match FIFO
3.8. Asserting Reset x
3.8.1. Reset Signal Requirements 3.8.2. Power On Reset Requirements 3.8.3. Reset Signals—Block Level 3.8.4. Reset Signals—Descriptions 3.8.5. Status Signals—Descriptions 3.8.6. Run-time Reset Sequence—TX 3.8.7. Run-time Reset Sequence—RX 3.8.8. Run-time Reset Sequence—TX + RX 3.8.9. Run-time Reset Sequence—TX with FEC
3.8.8. Run-time Reset Sequence—TX + RX x
3.8.8.1. Run-time Reset Sequence Approximate Time Durations
3.11. Configuration Registers x
3.11.1. PMA and FEC Direct PHY Soft CSR Register Map 3.11.2. FHT PMA Register Map 3.11.3. FGT PMA Register Map 3.11.4. FEC Register Map 3.11.5. Lane Offset Address 3.11.6. Logical Avalon® Memory-Mapped Port Indexing
3.11.6. Logical Avalon® Memory-Mapped Port Indexing x
3.11.6.1. FGT PMA Lane Addressing Example 1 3.11.6.2. FGT PMA Lane Addressing Example 2
3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing x
3.13.1. Using Debug Endpoint Interface within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 3.13.2. Using JTAG to Avalon® Master Bridge Intel FPGA IP
3.13.1. Using Debug Endpoint Interface within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.13.1.1. RTL Connection Example for Debug Endpoint Avalon® Interface
3.13.2. Using JTAG to Avalon® Master Bridge Intel FPGA IP x
3.13.2.1. RTL Connection Example for JTAG to Avalon® Master Bridge Intel IP
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface x
3.14.1. FHT PMA 3.14.2. FGT PMA
3.14.1. FHT PMA x
3.14.1.1. Enabling Loopback 3.14.1.2. Enabling the PRBS Generator and Verifier 3.14.1.3. TX Equalizer Settings 3.14.1.4. TX Error Injection 3.14.1.5. RX Reconvergence 3.14.1.6. Preserving Unused Lanes
3.14.2. FGT PMA x
3.14.2.1. Direct Register Method 3.14.2.2. FGT Attribute Access Method
3.14.2.1. Direct Register Method x
3.14.2.1.1. Direct Register Method Example
3.14.2.2. FGT Attribute Access Method x
3.14.2.2.1. FGT Attribute Access Method Example 1 3.14.2.2.2. FGT Attribute Access Method Example 2
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP x
4.1. IP Parameters 4.2. IP Port List 4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies 4.4. Guidelines for F-Tile Reference and System PLL Clocks Intel® FPGA IP Usage
5. Implementing the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP x
5.1. IP Parameters 5.2. IP Port List 5.3. Hardware Flow Using the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP
6. F-tile PMA/FEC Direct PHY Design Implementation x
6.1. Implementing the F-tile PMA/FEC Direct PHY Design 6.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 6.3. Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 6.4. Instantiating the F-Tile Reference and System PLL Clocks Intel® FPGA IP 6.5. Enabling Custom Cadence Generation Ports and Logic 6.6. Connecting the F-tile PMA/FEC Direct PHY Design IP 6.7. Simulating the F-Tile PMA/FEC Direct PHY Design 6.8. F-tile Interface Planning
6.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
6.2.1. Setting General and Common Datapath Options 6.2.2. Setting TX Datapath Options 6.2.3. Setting RX Datapath Options
6.7. Simulating the F-Tile PMA/FEC Direct PHY Design x
6.7.1. PAM4 Encoding Schemes in Simulation
6.8. F-tile Interface Planning x
6.8.1. F-tile Interface Planner Usage Example
7. Supported Tools x
7.1. F-Tile Channel Placement Tool 7.2. F-Tile PMA and FEC Direct Port Mapping Calculator 7.3. F-Tile Clocking and Datapath Tool 7.4. F-Tile TX Equalizer Tool
8. Debugging F-Tile Transceiver Links x
8.1. F-Tile Transceiver Toolkit GUI 8.2. F-Tile Transceiver Debugging Flow Walkthrough 8.3. Transceiver Toolkit Parameter Settings 8.4. Troubleshooting Common Errors
8.1. F-Tile Transceiver Toolkit GUI x
8.1.1. Collection View
8.2. F-Tile Transceiver Debugging Flow Walkthrough x
8.2.1. Modifying the Design to Enable F-Tile Transceiver Debug 8.2.2. Programming the Design into an Intel FPGA 8.2.3. Loading the Design to the Transceiver Toolkit 8.2.4. Creating Transceiver Links 8.2.5. Running BER Tests 8.2.6. Running Eye Viewer Tests
1. F-tile Overview
2. F-tile Architecture
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP
5. Implementing the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP
6. F-tile PMA/FEC Direct PHY Design Implementation
7. Supported Tools
8. Debugging F-Tile Transceiver Links
9. F-tile Architecture and PMA and FEC Direct PHY IP User Guide Archives
10. Document Revision History for F-tile Architecture and PMA and FEC Direct PHY IP User Guide

3.3.2.1. TX PMA interface Parameters

Figure 60. TX PMA interface Parameters
Table 30.  TX PMA interface Parameters
Parameter Values Description
TX PMA Interface Parameters
TX PMA interface FIFO mode

Phase Compensation

Elastic

Selects the TX PMA Interface FIFO mode. Default value is Elastic.
Enable tx_pmaif_fifo_empty port On/Off Enables the port that indicates the TX PMA Interface FIFO's empty condition. Default value is Off.
Enable tx_pmaif_fifo_pfull port On/Off Enables the port that indicates the TX PMA Interface FIFO's partially full condition. Default value is Off.
TX Core Interface Parameters
Enable custom cadence generation ports and logic On/Off Enables optional custom cadence generation (CCG) logic and ports (tx_cadence, tx_cadence_fast_clk, tx_cadence_slow_clk). CCG logic can be enabled when Datapath clocking mode is set to System PLL. Default value is Off. Refer to Custom Cadence Generation Ports and Logic .
Enable tx_cadence_slow_clk_locked port On/Off

If tx_cadence_slow_clk is not directly coming from TX PLL (word clock/bond clock/user clock), but rather comes from another clock source, you must turn on the tx_cadence_slow_clk_locked port option in the parameter editor. tx_cadence_slow_clk_locked must be driven by the PLL locked output of the other PLL source used for slow clock. Default value is Off.

TX core interface FIFO mode

Phase Compensation

Elastic

Specifies the mode for the TX Core Interface FIFO. Default value is Phase Compensation. Elastic FIFO is only supported for PMA Clocking mode.
TX Tile Interface FIFO mode

Phase Compensation

Register

Specifies the mode for the TX Tile Interface FIFO. Default value is Phase Compensation.
Enable TX double width transfer

On/Off

 Enables double width TX data transfer mode. In this mode, the core logic can be clocked with half rate clock. Default value is Off.
TX core interface FIFO partially full threshold 10 Specifies the partially full threshold for the TX Core Interface FIFO. Default value is 10.
TX core interface FIFO partially empty threshold 2 Specifies the partially empty threshold for the TX Core Interface FIFO. Default value is 2.
Enable tx_fifo_full port On/Off Enables the optional tx_fifo_full status output port. This signal indicates when the TX core FIFO has reached the full threshold. This signal is synchronous with tx_clkout. Default value is Off.
Enable tx_fifo_empty port On/Off Enables the optional tx_fifo_empty status output port. This signal indicates when the TX core FIFO has reached the empty threshold. This signal is synchronous with tx_clkout. Default value is Off.
Enable tx_fifo_pfull port On/Off Enables the optional tx_fifo_pfull status output port. This signal indicates when the TX core FIFO has reached the specified partially full threshold. Default value is Off.
Enable tx_fifo_pempty port On/Off Enables the optional tx_fifo_pempty status output port. This signal indicates when the TX core FIFO has reached the specified partially empty threshold. Default value is Off.
Enable tx_dll_lock port On/Off Enables the optional tx_dll_lock status output port. Monitor this signal when the core interface FIFO is in elastic mode, and then wait for the tx_dll_lock port to assert before asserting the write enable bit for the core interface FIFO. This signal indicates when the TX DLL is locked for data transfer. Default value is Off. Refer to TX and RX Parallel Data Mapping Information for Different Configurations for the write enable bit.
Enable fgt_tx_beacon port On/Off Enables or disables the fgt_tx_beacon port. Default value is Off.
TX Clock Options
Selected tx_clkout clock source

Word Clock

Bond Clock

User Clock 1

User Clock 2

Sys PLL Clock

Sys PLL Clock Div2

Specifies the tx_clkout output port source. Default value is Sys PLL Clock Div2.
Frequency of tx_clkout Output Displays the frequency of tx_clkout in MHz based on tx_clkout source selection.
Frequency of tx_clkout2 Output Displays the frequency of tx_clkout2 in MHz based on tx_clkout2 source selection and tx_clkout2 clock divide by factor.
Enable tx_clkout2 port On/Off Enables the optional tx_clkout2 output clock. Default value is Off.
Selected tx_clkout2 clock source

Word Clock

Bond Clock

User Clock 1

User Clock 2

Sys PLL Clock

Sys PLL Clock Div2

Specifies the tx_clkout2 output port source. Default value is Word Clock.
tx_clkout2 clock div by 1, 2, 4 Selects the tx_clkout2 divider setting that divides out the tx_clkout2 output port source. Default value is 1.
Selected tx_coreclkin clock network

Dedicated Clock

Global Clock

Specifies the type of clock network to use to route the clock signal to tx_coreclkin port. Dedicated clock allows a higher maximum frequency between the FPGA fabric and the F-tile interface. The number of Dedicated Clock lines are limited. Default value is Dedicated Clock.
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