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1. F-tile Overview
2. F-tile Architecture
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP
5. Implementing the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP
6. F-tile PMA/FEC Direct PHY Design Implementation
7. Supported Tools
8. Debugging F-Tile Transceiver Links
9. F-tile Architecture and PMA and FEC Direct PHY IP User Guide Archives
10. Document Revision History for F-tile Architecture and PMA and FEC Direct PHY IP User Guide
2.1.1. FHT and FGT PMAs
2.1.2. 400G Hard IP and 200G Hard IP
2.1.3. PMA Data Rates
2.1.4. FEC Architecture
2.1.5. PCIe* Hard IP
2.1.6. Bonding Architecture
2.1.7. Deskew Logic
2.1.8. Embedded Multi-die Interconnect Bridge (EMIB)
2.1.9. IEEE 1588 Precision Time Protocol for Ethernet
2.1.10. Clock Networks
2.1.11. Reconfiguration Interfaces
2.2.1. PMA-to-Fracture Mapping
2.2.2. Determining Which PMA to Map to Which Fracture
2.2.3. Hard IP Placement Rules
2.2.4. IEEE 1588 Precision Time Protocol Placement Rules
2.2.5. Topologies
2.2.6. FEC Placement Rules
2.2.7. Clock Rules and Restrictions
2.2.8. Bonding Placement Rules
2.2.9. Preserving Unused PMA Lanes
2.2.2.1. Implementing One 200GbE-4 Interface with 400G Hard IP and FHT
2.2.2.2. Implementing One 200GbE-2 Interface with 400G Hard IP and FHT
2.2.2.3. Implementing One 100GbE-1 Interface with 400G Hard IP and FHT
2.2.2.4. Implementing One 100GbE-4 Interface with 400G Hard IP and FGT
2.2.2.5. Implementing One 10GbE-1 Interface with 200G Hard IP and FGT
2.2.2.6. Implementing Three 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.7. Implementing One 50GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.8. Implementing One 100GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.9. Implementing Two 100GbE-1 and One 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.10. Implementing 100GbE-1, 100GbE-2, and 50GbE-1 Interfaces with 400G Hard IP and FHT
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview
3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP
3.3. Configuring the IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting Reset
3.9. Bonding Implementation
3.10. Independent Port Configurations
3.11. Configuration Registers
3.12. Configurable Intel® Quartus® Prime Software Settings
3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. RS-FEC Signals
3.4.5. Custom Cadence Control and Status Signals
3.4.6. TX PMA Status Signals
3.4.7. RX PMA Status Signals
3.4.8. TX and RX PMA and Core Interface FIFO Signals
3.4.9. PMA Avalon® Memory Mapped Interface Signals
3.4.10. Datapath Avalon® Memory Mapped Interface Signals
3.5.1. Parallel Data Mapping Information
3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations
3.5.3. Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1)
3.5.4. Example of TX Parallel Data for PMA width = 64 (X=2)
3.5.5. Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Reset Signals—Descriptions
3.8.5. Status Signals—Descriptions
3.8.6. Run-time Reset Sequence—TX
3.8.7. Run-time Reset Sequence—RX
3.8.8. Run-time Reset Sequence—TX + RX
3.8.9. Run-time Reset Sequence—TX with FEC
6.1. Implementing the F-tile PMA/FEC Direct PHY Design
6.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
6.3. Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
6.4. Instantiating the F-Tile Reference and System PLL Clocks Intel® FPGA IP
6.5. Enabling Custom Cadence Generation Ports and Logic
6.6. Connecting the F-tile PMA/FEC Direct PHY Design IP
6.7. Simulating the F-Tile PMA/FEC Direct PHY Design
6.8. F-tile Interface Planning
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3.14.2.2.1. FGT Attribute Access Method Example 1
The following example demonstrates the steps to enable the FGT PMA PRBS checker and generator, when you configure the FGT PMA in internal serial loopback mode in physical lane 0 of a quad, using the FGT attribute access method.
- Assert rx_reset.
- Enable serial loopback:
- Write 0x6A040 to address 0x9003C.
- Poll address 0x90040 until bit 14 = 0 and bit 15 = 1.
- Write 0x62040 to address 0x9003C.
- Poll address 0x90040 until bit 14 = 0 and bit 15 = 0.
- Deassert rx_reset.
- Confirm the channel is in serial loopback:
- Read out register 0x4781C; bit 1 should be high if serial loopback is enabled.
- Check the FGT PMA’s status:
- Write 0x800D to address 0x9003C.
- Poll address 0x90040 until bit 15 = 1; bit 16 should also be high if the channel is located in physical local 0.
- Write 0x000D to address 0x9003C.
- Poll address 0x90040 until bit 15 = 0.
- Set the PRBS31 pattern for both the TX and RX PMAs:
- Write 0x30CA041 to address 0x9003C.
- Poll address 0x90040 until bit 15 = 1.
- Write 0x30C2041 to address 0x9003C.
- Poll address 0x90040 until bit 15 = 0.
- Set up the PMA to count the number of bit errors:
- Write 0x14A045 to address 0x9003C.
- Poll address 0x90040 until bit 15 = 1.
- Write 0x14C2045 to address 0x9003C.
- Poll address 0x90040 until bit 15 = 0.
Note: This example selects the PRBS31 pattern for both the TX and RX PMA lanes and hence bits [27:16] for register 0x9003C are set to 0x30C. To select other PRBS patterns, set bits [27:16] for register 0x9003C as follows:- PRBS7: 0x208
- PRBS9: 0x249
- PRBS11: 0x28A
- PRBS23: 0x2CB
- QPRBS13: 0x34D
- PRBS13Q: 0x820
- PRBS31Q: 0x861
- SSPR: 0x8A2
- SSPR1: 0x8E3
- SSPRQ: 0x924
- PRBS13: 0x965
- Start the test:
- Write 0x20A00F to address 0x9003C.
- Poll address 0x90040 until bit 15 = 1.
- Write 0x20200F to address 0x9003C.
- Poll address 0x90040 until bit 15 = 0.
- Check that the test is running:
- Write 0x8049 to address 0x9003C.
- Poll address 0x90040 until bit 15 = 1; bits 25:24 should be 0x1 to indicate the test is running.
- Write 0x0049 to address 0x9003C.
- Poll address 0x90040 until bit 15 = 0.
- Set up the PRBS generator to inject errors:
- Write 0x123A042 to address 0x9003C to inject 0x123 errors.
- Poll address 0x90040 until bit 15 = 1.
- Write 0x1232042 to address 0x9003C.
- Poll address 0x90040 until bit 15 = 0.
- Tell the PRBS generator to inject errors:
- Write 0x23A00F to address 0x9003C.
- Poll address 0x90040 until bit 15 = 1.
- Write 0x23200F to address 0x9003C.
- Poll address 0x90040 until bit 15 = 0.
- Stop the BER test:
- Write 0x21A00F to address 0x9003C.
- Poll address 0x90040 until bit 15 = 1.
- Write 0x21200F to address 0x9003C.
- Poll address 0x90040 until bit 15 = 0.
- Check the test completed successfully:
- Write 0x8049 to address 0x9003C.
- Poll address 0x90040 until bit 15 = 1; bits 25:24 should be 0x3.
- Write 0x0049 to address 0x9003C.
- Poll address 0x90040 until bit 15 = 0.
- Read out the 12 LSB of the error count:
- Write 0x804A to address 0x9003C.
- Poll address 0x90040 until bit 15 = 1; bits 27:16 represent the 12 LSBs of the error count.
- Write 0x004A to address 0x9003C.
- Poll address 0x90040 until bit 15 = 0.
- Read out bits 27:12 of the error count:
- Write 0x804B to address 0x9003C.
- Poll address 0x90040 until bit 15 = 1; bits 31:16 represent bits 27:12 of the error count.
- Write 0x004B to address 0x9003C.
- Poll address 0x90040 until bit 15 = 0.
- Read out bits 31:28 of the error count:
- Write 0x804C to address 0x9003C.
- Poll address 0x90040 until bit 15 = 1; bits 19:16 represent bits 31:28 of the error count.
- Write 0x004C to address 0x9003C.
- Poll address 0x90040 until bit 15 = 0.
- Finish checking the PRBS and BER test:
- Write 0xA041 to address 0x9003C.
- Poll address 0x90040 until bit 15 = 1.
- Write 0x2041 to address 0x9003C.
- Poll address 0x90040 until bit 15 = 0.