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1. F-tile Overview
2. F-tile Architecture
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP
5. Implementing the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP
6. F-tile PMA/FEC Direct PHY Design Implementation
7. Supported Tools
8. Debugging F-Tile Transceiver Links
9. F-tile Architecture and PMA and FEC Direct PHY IP User Guide Archives
10. Document Revision History for F-tile Architecture and PMA and FEC Direct PHY IP User Guide
2.1.1. FHT and FGT PMAs
2.1.2. 400G Hard IP and 200G Hard IP
2.1.3. PMA Data Rates
2.1.4. FEC Architecture
2.1.5. PCIe* Hard IP
2.1.6. Bonding Architecture
2.1.7. Deskew Logic
2.1.8. Embedded Multi-die Interconnect Bridge (EMIB)
2.1.9. IEEE 1588 Precision Time Protocol for Ethernet
2.1.10. Clock Networks
2.1.11. Reconfiguration Interfaces
2.2.1. PMA-to-Fracture Mapping
2.2.2. Determining Which PMA to Map to Which Fracture
2.2.3. Hard IP Placement Rules
2.2.4. IEEE 1588 Precision Time Protocol Placement Rules
2.2.5. Topologies
2.2.6. FEC Placement Rules
2.2.7. Clock Rules and Restrictions
2.2.8. Bonding Placement Rules
2.2.9. Preserving Unused PMA Lanes
Unused PMA Lanes in a Completely Unused F-tile
Unused PMA lanes in a Partially Used F-tile
2.2.2.1. Implementing One 200GbE-4 Interface with 400G Hard IP and FHT
2.2.2.2. Implementing One 200GbE-2 Interface with 400G Hard IP and FHT
2.2.2.3. Implementing One 100GbE-1 Interface with 400G Hard IP and FHT
2.2.2.4. Implementing One 100GbE-4 Interface with 400G Hard IP and FGT
2.2.2.5. Implementing One 10GbE-1 Interface with 200G Hard IP and FGT
2.2.2.6. Implementing Three 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.7. Implementing One 50GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.8. Implementing One 100GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.9. Implementing Two 100GbE-1 and One 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.10. Implementing 100GbE-1, 100GbE-2, and 50GbE-1 Interfaces with 400G Hard IP and FHT
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview
3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP
3.3. Configuring the IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting Reset
3.9. Bonding Implementation
3.10. Independent Port Configurations
3.11. Configuration Registers
3.12. Configurable Intel® Quartus® Prime Software Settings
3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. RS-FEC Signals
3.4.5. Custom Cadence Control and Status Signals
3.4.6. TX PMA Status Signals
3.4.7. RX PMA Status Signals
3.4.8. TX and RX PMA and Core Interface FIFO Signals
3.4.9. PMA Avalon® Memory Mapped Interface Signals
3.4.10. Datapath Avalon® Memory Mapped Interface Signals
3.5.1. Parallel Data Mapping Information
3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations
3.5.3. Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1)
3.5.4. Example of TX Parallel Data for PMA width = 64 (X=2)
3.5.5. Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Reset Signals—Descriptions
3.8.5. Status Signals—Descriptions
3.8.6. Run-time Reset Sequence—TX
3.8.7. Run-time Reset Sequence—RX
3.8.8. Run-time Reset Sequence—TX + RX
3.8.9. Run-time Reset Sequence—TX with FEC
6.1. Implementing the F-tile PMA/FEC Direct PHY Design
6.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
6.3. Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
6.4. Instantiating the F-Tile Reference and System PLL Clocks Intel® FPGA IP
6.5. Enabling Custom Cadence Generation Ports and Logic
6.6. Connecting the F-tile PMA/FEC Direct PHY Design IP
6.7. Simulating the F-Tile PMA/FEC Direct PHY Design
6.8. F-tile Interface Planning
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2.2.9. Preserving Unused PMA Lanes
You must preserve the unused FHT and FGT PMA lanes that you plan to use later in your design to ensure no degradation in the PMA lane performance or maximum data rate during the period of use.
To preserve the performance of unused PMA lanes, the Intel® Quartus® Prime software can program the unused PMA lanes, such that the analog circuitry in their transmit and receive stages toggles at a low data rate.
Unused PMA lanes may appear in any of the following ways in the F-tile:
- Unused PMA lanes in a completely unused F-tile.
- Unused PMA lanes in a partially used F-tile.
Unused PMA Lanes in a Completely Unused F-tile
You must either preserve the completely unused F-tile with .qsf assignments or ground the power rails. If you do not plan to use the F-tile in the future and do not want to preserve the PMA lanes:
- You must tie the various F-tile power rails to ground to save power.
- You must not use .qsf assignments shown below in your project, to preserve the F-tile.
To preserve a completely unused F-tile to use it later:
- You must configure and power the F-tile and connect all power rails to the appropriate power supplies.
- You must use .qsf assignments in your project to preserve the unused F-tile.
You must use one of the .qsf assignments shown below to preserve unused lanes in the F-tile.
To preserve all unused PMA lanes in a single F-tile in a package, use the following single pin F-tile .qsf:
set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to <pinname>
Example:
set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to JW83
- <pinname> identifies the corresponding unused F-tile for preservation.
- Preserves the entire F-tile with a single pin. Pin can be specified on any lane, even if you do not connect the pin on the board.
- You can also use this .qsf assignment multiple times with corresponding pins from each F-tile to preserve multiple unused F-tiles.
If you have multiple unused tiles (including all unused F-tiles and other tiles such as R-tiles in a package), you can use the following global .qsf assignment to preserve all unused PMA lanes in all unused tiles in a package:
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON
Note: Do not use this .qsf assignment if you do not need to preserve all the unused tiles and have tied the power rails to ground for some of the tiles. This can result in a configuration error.
Example cases:
- You have 4 tiles in a package – one partially used tile and three others you want to preserve. You can use the global .qsf assignment to preserve the three tiles.
- You have 4 tiles in a package – one partially used tile, one tile with the power rails tied to ground to save power and two other tiles that you want preserve. Do not use the global .qsf assignment, but instead you must use the single pin F-tile .qsf assignment to preserve those two tiles.
Unused PMA lanes in a Partially Used F-tile
If your design does not instantiate (does not use) a PMA lane, preservation of the unused PMA lane in the partially used F-tile takes place by default.
If you instantiate a PMA lane in your partially used F-tile design for future use, you must fulfill the following conditions:
- If the PMA reference clock is not available, then the PMA must be held in reset. For example, when you are using the HDMI IP.
- You must not send long periods of all zeros or all ones on the TX PMA lane. If the PMA is held in reset, you do not need to follow this rule.
- For the FHT PMA lanes, you must set cfg_preserve_enable (0xF0030[3:0]) to 4’b1111 to preserve the lanes. LSB is for lane 0 and MSB is for lane 3.