Visible to Intel only — GUID: iqo1548322095833
Ixiasoft
Design Flow
System Specification
Device Selection
Early System and Board Planning
Pin Connection Considerations for Board Design
I/O and Clock Planning
Design Entry
Design Implementation, Analysis, Optimization, and Verification
Document Revision History for Intel® Cyclone® 10 LP Device Design Guidelines
Visible to Intel only — GUID: iqo1548322095833
Ixiasoft
Signal Integrity Considerations
Signal integrity considerations include detailed board design guidelines, as well as a few guidelines related to VREF pins, SSN, and I/O termination.