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Design Flow
System Specification
Device Selection
Early System and Board Planning
Pin Connection Considerations for Board Design
I/O and Clock Planning
Design Entry
Design Implementation, Analysis, Optimization, and Verification
Document Revision History for Intel® Cyclone® 10 LP Device Design Guidelines
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Other Configuration Pins
Number | Done? | Checklist Item |
---|---|---|
1 | Hold nCE (chip enable) low during configuration, initialization, and user mode. |
In a single-device configuration or JTAG programming, tie nCE low. In a multi-device configuration, tie nCE low on the first device and connect its nCEO pin to the nCE pin on the next device in the chain.