Intel Cyclone 10 LP Device Design Guidelines

ID 683861
Date 3/28/2019
Public
Document Table of Contents

PLL Feature Guidelines

Table 47.  PLL Feature Guidelines Checklist
Number Done? Checklist Item
1   Enable PLL features and check settings in the parameter editor.

Based on your system requirements, define the required clock frequencies for your FPGA design, and the input frequencies available to the FPGA. Use these specifications to determine your PLL scheme. Use the ALTPLL IP parameter editor in the Intel® Quartus® Prime Standard Edition to enter your settings, and check the results to verify whether particular features and input/output frequencies can be implemented in a particular PLL.

Intel® Cyclone® 10 LP device PLLs support several features for general-purpose clock management including clock feedback modes and switchover.