Intel Cyclone 10 LP Device Design Guidelines

ID 683861
Date 3/28/2019
Public
Document Table of Contents

Selectable Standards and Flexible I/O Banks

Table 43.  Selectable Standards and Flexible I/O Banks Checklist
Number Done? Checklist Item
1   Select a suitable signaling type and I/O standard for each I/O pin.
2   Ensure that the appropriate I/O standard support is supported in the targeted I/O bank.
3   Place I/O pins that share voltage levels in the same I/O bank.
4   Verify that all output signals in each I/O bank are intended to drive out at the bank’s VCCIO voltage level.
5   Verify that all voltage-referenced signals in each I/O bank are intended to use the bank’s VREF voltage level.
6   Check the I/O bank support for LVDS features. Different I/O banks include different support for LVDS signaling.

Intel® Cyclone® 10 LP devices have eight I/O banks. All differential I/O standards are supported in all banks. The only exception is HSTL-12 Class II, which is only supported in column I/O banks.

You can assign I/O standards and make other I/O-related settings in the Pin Planner.

The board must supply each bank with one VCCIO voltage level for every VCCIO pin in the bank. Each I/O bank is powered by the VCCIO pins of that particular bank and is independent of the VCCIO power supply of other I/O banks. A single I/O bank supports output signals that are driving at the same voltage as the VCCIO power supply. An I/O bank can simultaneously support any number of input signals with different I/O standards, with some exceptions for voltage-referenced inputs. Voltage-referenced standards are supported in an I/O bank using any number of single-ended or differential standards, as long as they use the same VREF and VCCIO values.

When you use the VREF pins as regular I/Os, they have higher pin capacitance than regular user I/O pins. This has an impact on the timing if the pins are used as inputs and outputs.