Intel Cyclone 10 LP Device Design Guidelines

ID 683861
Date 3/28/2019
Public
Document Table of Contents

Document Revision History for Intel® Cyclone® 10 LP Device Design Guidelines

Document Version Changes
2019.03.28 Removed the information about on-die decoupling capacitors from the Decoupling Capacitors section. Intel® Cyclone® 10 LP devices do not have on-die decoupling capacitors.
2019.01.25
  • Rebranded as Intel.
  • Updated the following terms:
    • Changed Qsys to Platform Designer
    • Changed OpenCore Plus to Intel FPGA IP Evaluation Mode
    • Changed TimeQuest Timing Analyzer to Timing Analyzer
  • Removed the information about power sequencing from the Device Power-up section. Power sequencing is not applicable for Intel® Cyclone® 10 LP devices.
  • Added conditions to use VCCIO or VCCA when powering JTAG pins in Intel® Cyclone® 10 LP devices in the Download Cable Operating Voltage section.
  • Removed information about the BluePrint Platform Designer feature in the Making FPGA Pin Assignments section. This feature is no longer supported in the Intel® Quartus® Prime Standard Edition software.
  • Removed information about the Early Timing Estimation feature from the Area and Timing Optimization section. This feature is no longer supported in the Intel® Quartus® Prime Standard Edition software.
Date Version Changes
May 2017 2017.05.08 Initial release.