Visible to Intel only — GUID: yei1548145440481
Ixiasoft
Visible to Intel only — GUID: yei1548145440481
Ixiasoft
I/O and Clock Planning
Planning and allocating I/O and clock resources is an important task with the high pin counts and advanced clock management features in Intel® Cyclone® 10 LP devices. Various considerations are important to effectively plan the available I/O resources to maximize utilization and prevent issues related to signal integrity. Good clock management systems are also crucial to the performance of an FPGA design.
The I/O and clock connections of your FPGA affect the rest of your system and board design, so it is important to plan these connections early in your design cycle.