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Design Flow
System Specification
Device Selection
Early System and Board Planning
Pin Connection Considerations for Board Design
I/O and Clock Planning
Design Entry
Design Implementation, Analysis, Optimization, and Verification
Document Revision History for Intel® Cyclone® 10 LP Device Design Guidelines
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Configuration Features
Number | Done? | Checklist Item |
---|---|---|
1 | Ensure your configuration scheme and board support the required features: design security, remote upgrades, single event upset (SEU) mitigation. |
Intel® Cyclone® 10 LP devices have a built-in dedicated circuitry for error detection and correction. When enabled, this feature checks for SEUs continuously and automatically. This allows you to confirm that the configuration data stored in a Intel® Cyclone® 10 LP device is correct and alerts the system to a configuration error.
To take advantage of the SEU mitigation features, turn on Enable error detection CRC in the Device and Pin Options dialog box of the Intel® Quartus® Prime Standard Edition software. Use the CRC_ERROR pin to flag errors and design your system to take the appropriate action. If not enabled for the CRC function, the CRC_ERROR pin is available as a user I/O pin.
Note: The SEU mitigation feature is available in all Intel® Cyclone® 10 LP devices with 1.2 V core voltage.