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Design Flow
System Specification
Device Selection
Early System and Board Planning
Pin Connection Considerations for Board Design
I/O and Clock Planning
Design Entry
Design Implementation, Analysis, Optimization, and Verification
Document Revision History for Intel® Cyclone® 10 LP Device Design Guidelines
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Design Flow
Stages of the Design Flow | Description |
---|---|
System Specification | Planning design specifications, IP selection |
Device Selection | Device information, determining device variant and density, package offerings, migration, speed grade |
Early System and Board Planning | Early power estimation, thermal management option, planning for configuration scheme, planning for on-chip debugging |
Pin Connection Considerations for Board Design | Power-up, power pins, PLL connections, decoupling capacitors, configuration pins, signal integrity, board-level verification |
I/O and Clock Planning | Pin assignments, early pin planning, I/O features and connections, memory interfaces, clock and PLL selection, simultaneous switching noise (SSN) |
Design Entry | Coding styles and design recommendations, Platform Designer (Standard), planning for hierarchical or team-based design |
Design Implementation, Analysis, Optimization, and Verification | Synthesis tool, device utilization, messages, timing constraints and analysis, area and timing optimization, compilation time, verification, power analysis and optimization |
Figure 1. Intel® Cyclone® 10 LP Device Design Flow