Intel Cyclone 10 LP Device Design Guidelines

ID 683861
Date 3/28/2019
Public
Document Table of Contents

Clock Trace Signal Integrity

Table 26.  Clock Trace Signal Integrity Checklist
Number Done? Checklist Item
1   Design configuration clock traces to be noise-free.

Board trace for clocks used in configuration, for example TCK and DCLK clock input, should produce clean signals with no overshoot, undershoot, or ringing. When designing the board, lay out the configuration clock traces with the same techniques used to lay out a clock line. Any overshoot, undershoot, ringing, or other noise on the clock signal can cause configuration failure.