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Design Flow
System Specification
Device Selection
Early System and Board Planning
Pin Connection Considerations for Board Design
I/O and Clock Planning
Design Entry
Design Implementation, Analysis, Optimization, and Verification
Document Revision History for Intel® Cyclone® 10 LP Device Design Guidelines
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Clock Outputs
Number | Done? | Checklist Item |
---|---|---|
1 | Check that the PLL offers the required number of clock outputs and use dedicated clock output pins. |
You can connect clock outputs to dedicated clock output pins or dedicated clock networks. There is no dedicated clock out pin for fractional PLL. I/O PLL can connect to a clock network or a dedicated clock pin.