Visible to Intel only — GUID: kly1463120146040
Ixiasoft
Visible to Intel only — GUID: kly1463120146040
Ixiasoft
8.6.6. Systolic/Chainout Tab
Parameter | IP Generated Parameter | Value | Default Value | Description |
---|---|---|---|---|
Enable chainout adder | chainout_adder | YES, NO |
NO | Select YES to enable chainout adder module. |
What is the chainout adder operation type? | chainout_adder_direction | ADD, SUB |
ADD | Specifies the chainout adder operation. For subtraction operation, SIGNED must be selected for What is the representation format for Multipliers A inputs? and What is the representation format for Multipliers B inputs? in the Multipliers Tab. |
Enable ‘negate’ input for chainout adder? | Port_negate | PORT_USED, PORT_UNUSED |
PORT_UNUSED | Select PORT_USED to enable negate input signal. This parameter is invalid when chainout adder is disabled. |
Register ‘negate’ input? | negate_register | UNREGISTERED, CLOCK0, CLOCK1, CLOCK2, CLOCK3 |
UNREGISTERED | To enable the input register for negate input signal and specifies the input clock signal for negate register. Select UNREGISTERED if the negate input register to is not needed
This parameter is invalid when you select:
|
What is the source for asynchronous clear input? | negate_aclr | NONE ACLR0 ACLR1 |
NONE | Specifies the asynchronous clear source for the negate register.
This parameter is invalid when you select:
|
What is the source for synchronous clear input? | negate_sclr | NONE SCLR0 SCLR1 |
NONE | Specifies the synchronous clear source for the negate register.
This parameter is invalid when you select:
|
Systolic Delay | ||||
Enable systolic delay registers | gui_systolic_delay | On Off |
Off | Select this option to enable systolic mode. This parameter is available when you select 2, or 4 for What is the number of multipliers? parameter. You must enable the Register output of the adder unit to use the systolic delay registers. |
What is the source for clock input? | gui_systolic_delay_clock | CLOCK0, CLOCK1, CLOCK2, |
CLOCK0 | Specifies the input clock signal for systolic delay register. You must select enable systolic delay registers to enable this option. |
What is the source for asynchronous clear input? | gui_systolic_delay_aclr | NONE ACLR0 ACLR1 |
NONE | Specifies the asynchronous clear source for the systolic delay register. You must select enable systolic delay registers to enable this option. |
What is the source for synchronous clear input? | gui_systolic_delay_sclr | NONE SCLR0 SCLR1 |
NONE | Specifies the synchronous clear source for the systolic delay register. You must select enable systolic delay registers to enable this option. |