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1. Intel FPGA Integer Arithmetic IP Cores
2. LPM_COUNTER (Counter) IP Core
3. LPM_DIVIDE (Divider) Intel FPGA IP Core
4. LPM_MULT (Multiplier) IP Core
5. LPM_ADD_SUB (Adder/Subtractor)
6. LPM_COMPARE (Comparator)
7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core
8. Intel FPGA Multiply Adder IP Core
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core
10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core
11. ALTMULT_ADD (Multiply-Adder) IP Core
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core
13. ALTSQRT (Integer Square Root) IP Core
14. PARALLEL_ADD (Parallel Adder) IP Core
15. Integer Arithmetic IP Cores User Guide Document Archives
16. Document Revision History for Intel FPGA Integer Arithmetic IP Cores User Guide
7.1. ALTECC Encoder Features
7.2. Verilog HDL Prototype (ALTECC_ENCODER)
7.3. Verilog HDL Prototype (ALTECC_DECODER)
7.4. VHDL Component Declaration (ALTECC_ENCODER)
7.5. VHDL Component Declaration (ALTECC_DECODER)
7.6. VHDL LIBRARY_USE Declaration
7.7. Encoder Ports
7.8. Decoder Ports
7.9. Encoder Parameters
7.10. Decoder Parameters
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4.7.3. Pipelining
Parameter | Value | Default Value | Description |
---|---|---|---|
Do you want to pipeline the function? | |||
Pipeline | No Yes |
No | Select Yes to enable pipeline register to the multiplier's output. Enabling the pipeline register adds extra latency to the output. |
Latency | Any value greater than 0. | 1 | Specify the desired output latency in clock cycle. |
Clear Signal Type | NONE ACLR SCLR |
NONE | Specify the type of reset for the pipeline register. Select NONE if you do not use any pipeline register. Select ACLR to use asynchronous clear for the pipeline register. This will generate ACLR port. Select SCLR to use synchronous clear for the pipeline register. This will generate SCLR port. |
Create a 'clken' clock enable clock | — | — | Specifies active high clock enable for the clock port of the pipeline register |
What type of optimization do you want? | |||
Type | Default Speed Area |
Default | Specify the desired optimization for the IP core. Select Default to let Intel® Quartus® Prime software to determine the best optiomization for the IP core. |