Intel FPGA Integer Arithmetic IP Cores User Guide

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ID 683490
Date 10/05/2020
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Document Table of Contents
Document Table of Contents x
1. Intel FPGA Integer Arithmetic IP Cores 2. LPM_COUNTER (Counter) IP Core 3. LPM_DIVIDE (Divider) Intel FPGA IP Core 4. LPM_MULT (Multiplier) IP Core 5. LPM_ADD_SUB (Adder/Subtractor) 6. LPM_COMPARE (Comparator) 7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core 8. Intel FPGA Multiply Adder IP Core 9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core 10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core 11. ALTMULT_ADD (Multiply-Adder) IP Core 12. ALTMULT_COMPLEX (Complex Multiplier) IP Core 13. ALTSQRT (Integer Square Root) IP Core 14. PARALLEL_ADD (Parallel Adder) IP Core 15. Integer Arithmetic IP Cores User Guide Document Archives 16. Document Revision History for Intel FPGA Integer Arithmetic IP Cores User Guide
2. LPM_COUNTER (Counter) IP Core x
2.1. Features 2.2. Verilog HDL Prototype 2.3. VHDL Component Declaration 2.4. VHDL LIBRARY_USE Declaration 2.5. Ports 2.6. Parameters
3. LPM_DIVIDE (Divider) Intel FPGA IP Core x
3.1. Features 3.2. Verilog HDL Prototype 3.3. VHDL Component Declaration 3.4. VHDL LIBRARY_USE Declaration 3.5. Ports 3.6. Parameters
4. LPM_MULT (Multiplier) IP Core x
4.1. Features 4.2. Verilog HDL Prototype 4.3. VHDL Component Declaration 4.4. VHDL LIBRARY_USE Declaration 4.5. Signals 4.6. Parameters for Stratix V, Arria V, Cyclone V, and Intel® Cyclone® 10 LP Devices 4.7. Parameters for Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX Devices
4.6. Parameters for Stratix V, Arria V, Cyclone V, and Intel® Cyclone® 10 LP Devices x
4.6.1. General Tab 4.6.2. General 2 Tab 4.6.3. Pipelining Tab
4.7. Parameters for Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX Devices x
4.7.1. General Tab 4.7.2. General 2 Tab 4.7.3. Pipelining
5. LPM_ADD_SUB (Adder/Subtractor) x
5.1. Features 5.2. Verilog HDL Prototype 5.3. VHDL Component Declaration 5.4. VHDL LIBRARY_USE Declaration 5.5. Ports 5.6. Parameters
6. LPM_COMPARE (Comparator) x
6.1. Features 6.2. Verilog HDL Prototype 6.3. VHDL Component Declaration 6.4. VHDL LIBRARY_USE Declaration 6.5. Ports 6.6. Parameters
7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core x
7.1. ALTECC Encoder Features 7.2. Verilog HDL Prototype (ALTECC_ENCODER) 7.3. Verilog HDL Prototype (ALTECC_DECODER) 7.4. VHDL Component Declaration (ALTECC_ENCODER) 7.5. VHDL Component Declaration (ALTECC_DECODER) 7.6. VHDL LIBRARY_USE Declaration 7.7. Encoder Ports 7.8. Decoder Ports 7.9. Encoder Parameters 7.10. Decoder Parameters
8. Intel FPGA Multiply Adder IP Core x
8.1. Features 8.2. Verilog HDL Prototype 8.3. VHDL Component Declaration 8.4. VHDL LIBRARY_USE Declaration 8.5. Signals 8.6. Parameters
8.1. Features x
8.1.1. Pre-adder 8.1.2. Systolic Delay Register 8.1.3. Pre-load Constant 8.1.4. Double Accumulator
8.1.1. Pre-adder x
8.1.1.1. Pre-adder Simple Mode 8.1.1.2. Pre-adder Coefficient Mode 8.1.1.3. Pre-adder Input Mode 8.1.1.4. Pre-adder Square Mode 8.1.1.5. Pre-adder Constant Mode
8.6. Parameters x
8.6.1. General Tab 8.6.2. Extra Modes Tab 8.6.3. Multipliers Tab 8.6.4. Preadder Tab 8.6.5. Accumulator Tab 8.6.6. Systolic/Chainout Tab 8.6.7. Pipelining Tab
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core x
9.1. Features 9.2. Verilog HDL Prototype 9.3. VHDL Component Declaration 9.4. Ports 9.5. Parameters
10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core x
10.1. Features 10.2. Verilog HDL Prototype 10.3. VHDL Component Declaration 10.4. VHDL LIBRARY_USE Declaration 10.5. Ports 10.6. Parameters
11. ALTMULT_ADD (Multiply-Adder) IP Core x
11.1. Features 11.2. Verilog HDL Prototype 11.3. VHDL Component Declaration 11.4. VHDL LIBRARY_USE Declaration 11.5. Ports 11.6. Parameters
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core x
12.1. Complex Multiplication 12.2. Canonical Representation 12.3. Conventional Representation 12.4. Features 12.5. Verilog HDL Prototype 12.6. VHDL Component Declaration 12.7. VHDL LIBRARY_USE Declaration 12.8. Signals 12.9. Parameters
13. ALTSQRT (Integer Square Root) IP Core x
13.1. Features 13.2. Verilog HDL Prototype 13.3. VHDL Component Declaration 13.4. VHDL LIBRARY_USE Declaration 13.5. Ports 13.6. Parameters
14. PARALLEL_ADD (Parallel Adder) IP Core x
14.1. Feature 14.2. Verilog HDL Prototype 14.3. VHDL Component Declaration 14.4. VHDL LIBRARY_USE Declaration 14.5. Ports 14.6. Parameters
1. Intel FPGA Integer Arithmetic IP Cores
2. LPM_COUNTER (Counter) IP Core
3. LPM_DIVIDE (Divider) Intel FPGA IP Core
4. LPM_MULT (Multiplier) IP Core
5. LPM_ADD_SUB (Adder/Subtractor)
6. LPM_COMPARE (Comparator)
7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core
8. Intel FPGA Multiply Adder IP Core
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core
10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core
11. ALTMULT_ADD (Multiply-Adder) IP Core
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core
13. ALTSQRT (Integer Square Root) IP Core
14. PARALLEL_ADD (Parallel Adder) IP Core
15. Integer Arithmetic IP Cores User Guide Document Archives
16. Document Revision History for Intel FPGA Integer Arithmetic IP Cores User Guide

16. Document Revision History for Intel FPGA Integer Arithmetic IP Cores User Guide

Document Version Intel® Quartus® Prime Version Changes
2020.10.05 20.3 Added a note to removed ALTMEMMULT support in Intel® Quartus® Prime Pro Edition software.
2020.04.30 17.1
  • Updated values for Which multiplier implementation should be used? parameter for LPM_MULT IP core in the Parameters for Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX Devices topic.
Date Version Changes
November 2017 2017.11.24
  • Rebranded ALTERA_MULT_ADD IP core name to Intel FPGA Multiply Adder for Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices.
  • Reverted the behavior of sload_accum and accum_sload signals in Intel FPGA Multiply Adder or ALTERA_MULT_ADD Input Signals.
  • Added Intel® Stratix® 10 devices in the List of IP Cores table.
  • Removed Design Example Files section.
  • Added a note for the first multiplier chainin signal in Systolic Delay Register.
June 2017 2017.06.19
  • Rebranded as Intel.
  • Added support for Cyclone 10 GX and Cyclone 10 LP devices.
  • Removed outdated design example information.
  • Updated sload_accum and accum_sload signals behavior in the ALTERA_MULT_ADD Input Signals table.
June 2016 2016.06.10
  • Added separate parameters table for Arria 10 devices.
  • Replaced ip-generated parameter names with GUI parameter names for LPM_MULT, ALTERA_MULT_ADD and ALTMULT_COMPLEX IP cores.
  • Added synchronous clear support for input, pipeline, and output registers LPM_MULT in Arria 10 devices, ALTERA_MULT_ADD for all devices and ALTMULT_COMPLEX for Arria 10 devices.
  • Added new parameters in LPM_MULT and ALTMULT_COMPLEX IP cores (Arria 10 devices) and ALTERA_MULT_ADD (for all devices) to enable users to select synchronous clear feature.
  • Removed resource tables for all Integer Arithmetic IP cores.
November 2015 2015.11.18
  • Corrected LPM_COUNTER VHDL component declaration.
  • Added device support list to List of IP Cores table.
  • Removed Stratix V, Arria V and Cyclone V devices support for ALTMULT_ACCUM and ALTMULT_ADD IP cores.
  • Removed Cyclone II, Cyclone III, Stratix II, and Stratix III because these devices are no longer supported for all the integer arithmetic IP cores.
  • Change COEFFSEL[]_REGISTER parameter name to COEFSEL[]_REGISTER and COEFFSEL[]_ACLR parameter name to COEFSEL[]_ACLR.
  • Added description in REPRESENTATION_A and REPRESENTATION_B parameters to clarify only signed input representation is supported for Stratix V, Arria V, Cyclone V, and Arria 10 devices.
  • Added LPM_ADD_SUB and LPM_COMPARE IP cores information.
  • Added links to Introduction to Altera IP Cores, Creating Version-Independent IP and Qsys Simulation Scripts, and Project Management Best Practices.
  • Changed instances of Quartus II to Quartus Prime.
December, 2014 2014.12.19
  • Removed the LPM_ADD_SUB and LPM_COMPARE IPs because these IPs are no longer supported.
  • Added a note to clarify that when building multipliers larger than the natively supported size there may be a performance impact resulting from the cascading of the DSP blocks in LPM_MULT, ALTERA_MULT_ADD, ALTMULT_ACCUM, ALTMULT_ADD, and ALTMULT_COMPLEX IP cores.
  • Added information about the Create a ‘sync_e’ port parameter and the sync_e signal for ALTECC_DECODER IP core.
  • Removed sconst port information as the port is no longer available for LPM_COUNTER IP core.
  • Provided an example to use the LPM_HINT parameter.
August, 2014 2014.08.18
  • Updated parameterization steps for legacy and latest parameter editors.
  • Added note for IP cores that do not support Arria 10 designs.
  • Added device migration information.
June 2014 5.0
  • Replaced MegaWizard Plug-In Manager information with IP Catalog.
  • Added standard information about upgrading IP cores.
  • Added standard installation and licensing information.
  • Removed outdated device support level information. IP core device support is now available in IP Catalog and parameter editor.
June 2013 4.0
  • Added Intel FPGA Multiply Adder IP Core section.
  • Removed the following obsoleted megafunctions: LPM_ABS, ALTACCUMULATE, ALTMULT_ACCUM, ALTMULT_ADD.
  • Updated ALTMULT_ACCUM (Multiply-Accumulate) on page 10-1 to include an obsolescence note and remove Arria V, Cyclone V, and Stratix V devices information.
  • Updated ALTMULT_ADD (Multiply-Adder) on page 11-1 to include an obsolescence note and remove Arria V, Cyclone V, and Stratix V devices information.
February 2013 3.1
  • Updated Table 52 on page 63 to include Stratix V information for accum_sload port.
  • Updated Table 54 on page 65 to include Stratix V information for PORT_SIGNA and PORT_SIGNB parameters.
February 2012 3.0
  • Added Arria V and Cyclone V device support.
  • Updated the parameter description for the following section:
    • ALTMULT_ACCUM (Multiply-Accumulate)
    • ALTMULT_ADD (Multiply-Add)
  • Added the Double Accumulator section.
July 2010 2.0
  • Updated architecture information for the following sections:
    • ALTMULT_ACCUM (Multiply-Accumulate)
    • ALTMULT_ADD (Multiply-Add)
    • ALTMULT_COMPLEX (Complex Multiplier)
  • Added specification information for all megafunctions
November 2009 1.0 Initial release.
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