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1. Intel FPGA Integer Arithmetic IP Cores
2. LPM_COUNTER (Counter) IP Core
3. LPM_DIVIDE (Divider) Intel FPGA IP Core
4. LPM_MULT (Multiplier) IP Core
5. LPM_ADD_SUB (Adder/Subtractor)
6. LPM_COMPARE (Comparator)
7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core
8. Intel FPGA Multiply Adder IP Core
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core
10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core
11. ALTMULT_ADD (Multiply-Adder) IP Core
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core
13. ALTSQRT (Integer Square Root) IP Core
14. PARALLEL_ADD (Parallel Adder) IP Core
15. Integer Arithmetic IP Cores User Guide Document Archives
16. Document Revision History for Intel FPGA Integer Arithmetic IP Cores User Guide
7.1. ALTECC Encoder Features
7.2. Verilog HDL Prototype (ALTECC_ENCODER)
7.3. Verilog HDL Prototype (ALTECC_DECODER)
7.4. VHDL Component Declaration (ALTECC_ENCODER)
7.5. VHDL Component Declaration (ALTECC_DECODER)
7.6. VHDL LIBRARY_USE Declaration
7.7. Encoder Ports
7.8. Decoder Ports
7.9. Encoder Parameters
7.10. Decoder Parameters
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7.8. Decoder Ports
The following tables list the input and output ports for the ALTECC decoder IP core.
Port Name | Required | Description |
---|---|---|
data[] | Yes | Data input port. The size of the input port depends on the WIDTH_CODEWORD parameter value. |
clock | Yes | Clock input port that provides the clock signal to synchronize the encoding operation. The clock port is required when the LPM_PIPELINE value is greater than 0. |
clocken | No | Clock enable. If omitted, the default value is 1. |
aclr | No | Asynchronous clear input. The active high aclr signal can be used at any time to asynchronously clear the registers. |
Port Name | Required | Description |
---|---|---|
q[] | Yes | Decoded data output port. The size of the output port depends on the WIDTH_DATAWORD parameter value. |
err_detected | Yes | Flag signal to reflect the status of data received and specifies any errors found. |
err_corrected | Yes | Flag signal to reflect the status of data received. Denotes single-bit error found and corrected. You can use the data because it has already been corrected. |
err_fatal | Yes | Flag signal to reflect the status of data received. Denotes double-bit error found, but not corrected. You must not use the data if this signal is asserted. |
syn_e | No | An output signal which will go high whenever a single-bit error is detected on the parity bits. |