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1. Intel FPGA Integer Arithmetic IP Cores
2. LPM_COUNTER (Counter) IP Core
3. LPM_DIVIDE (Divider) Intel FPGA IP Core
4. LPM_MULT (Multiplier) IP Core
5. LPM_ADD_SUB (Adder/Subtractor)
6. LPM_COMPARE (Comparator)
7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core
8. Intel FPGA Multiply Adder IP Core
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core
10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core
11. ALTMULT_ADD (Multiply-Adder) IP Core
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core
13. ALTSQRT (Integer Square Root) IP Core
14. PARALLEL_ADD (Parallel Adder) IP Core
15. Integer Arithmetic IP Cores User Guide Document Archives
16. Document Revision History for Intel FPGA Integer Arithmetic IP Cores User Guide
7.1. ALTECC Encoder Features
7.2. Verilog HDL Prototype (ALTECC_ENCODER)
7.3. Verilog HDL Prototype (ALTECC_DECODER)
7.4. VHDL Component Declaration (ALTECC_ENCODER)
7.5. VHDL Component Declaration (ALTECC_DECODER)
7.6. VHDL LIBRARY_USE Declaration
7.7. Encoder Ports
7.8. Decoder Ports
7.9. Encoder Parameters
7.10. Decoder Parameters
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10.5. Ports
The following tables list the input and output ports for the ALTMULT_ACCUM IP core.
Port Name | Required | Description |
---|---|---|
accum_sload | No | Causes the value on the accumulator feedback path to go to zero (0) or to accum_sload_upper_data when concatenated with 0. If the accumulator is adding and the accum_sload port is high, then the multiplier output is loaded into the accumulator. If the accumulator is subtracting, then the opposite (negative value) of the multiplier output is loaded into the accumulator. |
aclr0 | No | The first asynchronous clear input. The aclr0 port is active high. |
aclr1 | No | The second asynchronous clear input. The aclr1 port is active high. |
aclr2 | No | The third asynchronous clear input. The aclr2 port is active high. |
aclr3 | No | The fourth asynchronous clear input. The aclr3 port is active high. |
addnsub | No | Controls the functionality of the adder. If the addnsub port is high, the adder performs an add function; if the addnsub port is low, the adder performs a subtract function. |
clock0 | No | Specifies the first clock input, usable by any register in the IP core. |
clock1 | No | Specifies the second clock input, usable by any register in the IP core. |
clock2 | No | Specifies the third clock input, usable by any register in the IP core. |
clock3 | No | Specifies the fourth clock input, usable by any register in the IP core. |
dataa[] | Yes | Data input to the multiplier. The size of the input port depends on the WIDTH_A parameter value. |
datab[] | Yes | Data input to the multiplier. The size of the input port depends on the WIDTH_B parameter value. |
ena0 | No | Clock enable for the clock0 port. |
ena1 | No | Clock enable for the clock1 port. |
ena2 | No | Clock enable for the clock2 port. |
ena3 | No | Clock enable for the clock3 port. |
signa | No | Specifies the numerical representation of the dataa[] port. If the signa port is high, the multiplier treats the dataa[] port as signed two's complement. If the signa port is low, the multiplier treats the dataa[] port as an unsigned number. |
signb | No | Specifies the numerical representation of the datab[] port. If the signb port is high, the multiplier treats the datab[] port as signed two's complement. If the signb port is low, the multiplier treats the datab[]port as an unsigned number. |
Port Name | Required | Description |
---|---|---|
sourcea | No | Input source for scan chain A and dynamically controls whether the scanina[] and dataa[] ports are fed to the multiplier. |
sourceb | No | Input source for scan chain B. |
Port Name | Required | Description |
---|---|---|
accum_round | No | Enables accumulator rounding. |
Port Name | Required | Description |
---|---|---|
overflow | No | Overflow port for the accumulator. |
result[] | Yes | Accumulator output port. The size of the output port depends on the WIDTH_RESULT parameter value. |
scanouta[] | No | Output of the first shift register. The size of the output port depends on the WIDTH_A parameter value. The parameter editor renames the scanouta[] port to shiftouta port. |
scanoutb[] | No | Output of the second shift register. The size of the input port depends on the WIDTH_B parameter value. The parameter editor renames the scanoutb[] port to shiftoutb port. |